Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation
S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, Z. Navabi, in: 2015 10th International Conference on Design &; Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015.
LibreCat: /record/29465
DOI: 10.1109/dtis.2015.7127373

Online self adjusting progressive age monitoring of timing variations
S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, Z. Navabi, in: 2015 10th International Conference on Design &; Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015.
LibreCat: /record/29466
DOI: 10.1109/dtis.2015.7127368

FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects
S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’14), IEEE, Seattle, Washington, USA, 2014.
LibreCat: /record/12977
DOI: 10.1109/test.2014.7035360

An off-line MDSI interconnect BIST incorporated in BS 1149.1
M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, Z. Navabi, in: 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014.
LibreCat: /record/46268
DOI: 10.1109/ets.2014.6847847

Improving polynomial datapath debugging with HEDs
S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, Z. Navabi, in: 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014.
LibreCat: /record/46267
DOI: 10.1109/ets.2014.6847797

Analyzing and Quantifying Fault Tolerance Properties
S. Hellebrand, in: 14th IEEE Latin American Test Workshop - (LATW’13), IEEE, Cordoba, Argentina, 2013.
LibreCat: /record/12979
DOI: 10.1109/latw.2013.6562662

BS 1149.1 extensions for an online interconnect fault detection and recovery
S. Sadeghi-Kohan, M. Namaki-Shoushtari, F. Javaheri, Z. Navabi, in: 2012 IEEE International Test Conference, IEEE, 2013.
LibreCat: /record/46271
DOI: 10.1109/test.2012.6401583

A new structure for interconnect offline testing
S. Sadeghi-Kohan, S. Keshavarz, F. Zokaee, F. Farahmandi, Z. Navabi, in: East-West Design &;amp; Test Symposium (EWDTS 2013), IEEE, 2013.
LibreCat: /record/46270
DOI: 10.1109/ewdts.2013.6673207

Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test
A. Cook, S. Hellebrand, M. E. Imhof, A. Mumtaz, H.-J. Wunderlich, in: 13th IEEE Latin American Test Workshop (LATW’12), IEEE, Quito, Ecuador, 2012, pp. 1–4.
LibreCat: /record/12980
DOI: 10.1109/latw.2012.6261229

Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test
A. Cook, S. Hellebrand, H.-J. Wunderlich, in: 17th IEEE European Test Symposium (ETS’12), IEEE, Annecy, France, 2012, pp. 1–6.
LibreCat: /record/12981
DOI: 10.1109/ets.2012.6233025

Diagnostic Test of Robust Circuits
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: 20th IEEE Asian Test Symposium (ATS’11), IEEE, New Delhi, India, 2011, pp. 285–290.
LibreCat: /record/12982
DOI: 10.1109/ats.2011.55

Towards Variation-Aware Test Methods
I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, P. Maxwell, in: 16th IEEE European Test Symposium Trondheim (ETS’11), IEEE, Trondheim, Norway, 2011.
LibreCat: /record/12984
DOI: 10.1109/ets.2011.51

Robuster Selbsttest mit Diagnose
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf,” Hamburg, Germany, 2011, pp. 48–53.
LibreCat: /record/13053

Virtual tester development using HDL/PLI
A. Kamran, N. Nemati, S. Sadeghi-Kohan, Z. Navabi, in: 2010 East-West Design &;amp; Test Symposium (EWDTS), IEEE, 2011.
LibreCat: /record/46272
DOI: 10.1109/ewdts.2010.5742156

Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), IEEE, Chicago, IL, USA, 2010.
LibreCat: /record/12987
DOI: 10.1109/dsnw.2010.5542612

Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz
M. Hunger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 81–88.
LibreCat: /record/13051

Variation-Aware Fault Modeling
F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 19th IEEE Asian Test Symposium (ATS’10), IEEE, Shanghai, China, 2010, pp. 87–93.
LibreCat: /record/12983
DOI: 10.1109/ats.2010.24

Efficient Test Response Compaction for Robust BIST Using Parity Sequences
T. Indlekofer, M. Schnittger, S. Hellebrand, in: 28th IEEE International Conference on Computer Design (ICCD’10), IEEE, Amsterdam, The Netherlands, 2010, pp. 480–485.
LibreCat: /record/12985
DOI: 10.1109/iccd.2010.5647648

The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems
M. Hunger, S. Hellebrand, in: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), IEEE, Kyoto, Japan, 2010, pp. 101–108.
LibreCat: /record/12986
DOI: 10.1109/dft.2010.19

Reusing NoC-Infrastructure for Test Data Compression
V. Froese, R. Ibers, S. Hellebrand, in: 28th IEEE VLSI Test Symposium (VTS’10), IEEE, Santa Cruz, CA, USA, 2010, pp. 227–231.
LibreCat: /record/12988
DOI: 10.1109/vts.2010.5469570