Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., &; Wunderlich, H.-J. (n.d.). Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. European Test Symposium, The Hague, Netherlands, May 20-24, 2024, 6.
LibreCat: /record/52744

Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., &; Wunderlich, H.-J. (n.d.). Vmin Testing under Variations: Defect vs. Fault Coverage. IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, 6.
LibreCat: /record/52742

Hellebrand, S., Sadeghi-Kohan, S., &; Wunderlich, H.-J. (n.d.). Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.
LibreCat: /record/52743

Wunderlich, H.-J., Jafarzadeh, H., &; Hellebrand, S. (n.d.). Robust Test of Small Delay Faults under  PVT-Variations. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.
LibreCat: /record/52745

Sadeghi-Kohan, S., Hellebrand, S., &; Wunderlich, H.-J. (2023). Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W).https://doi.org/10.1109/dsn-w58399.2023.00056 
LibreCat: /record/46739
DOI: 10.1109/dsn-w58399.2023.00056

Sadeghi-Kohan, S., Reimer, J. D., Hellebrand, S., &; Wunderlich, H.-J. (2023). Optimizing the Streaming of Sensor Data with Approximate Communication. IEEE Asian Test Symposium (ATS’23), October 2023. IEEE Asian Test Symposium (ATS’23).
LibreCat: /record/46738

Jafarzadeh, H., Klemme, F., Reimer, J. D., Najafi Haghi, Z. P.,  Amrouch, H., Hellebrand, S., &;  Wunderlich, H.-J. (2023). Robust Pattern Generation for Small Delay Faults under Process Variations. IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE International Test Conference (ITC’23), Anaheim, USA.
LibreCat: /record/45830

Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., &; Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020.
LibreCat: /record/19422

Sadeghi-Kohan, S., &; Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 38th IEEE VLSI Test Symposium (VTS).https://doi.org/10.1109/vts48691.2020.9107591 
LibreCat: /record/29200
DOI: 10.1109/vts48691.2020.9107591

Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich, H.-J., &; Weng, X. (2020). Logic Fault Diagnosis of Hidden Delay Defects. IEEE International Test Conference (ITC’20), November 2020.
LibreCat: /record/19421

Maaz, M. U., Sprenger, A., &; Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. 50th IEEE International Test Conference (ITC), 1–8.
LibreCat: /record/12918

Rezaeizadeh Rookerd, R., Sadeghi-Kohan, S., &; Navabi, Z. (2018). Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. Proceedings of the 2018 on Great Lakes Symposium on VLSI.https://doi.org/10.1145/3194554.3194599 
LibreCat: /record/29460
DOI: 10.1145/3194554.3194599

Sprenger, A., &; Hellebrand, S. (2018). Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &; Systems (DDECS).https://doi.org/10.1109/ddecs.2018.00020 
LibreCat: /record/4575
DOI: 10.1109/ddecs.2018.00020

Liu, C., Schneider, E., Kampmann, M., Hellebrand, S., &; Wunderlich, H.-J. (2018). Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. 27th IEEE Asian Test Symposium (ATS’18).https://doi.org/10.1109/ats.2018.00028 
LibreCat: /record/10575
DOI: 10.1109/ats.2018.00028

Sadeghi-Kohan, S., Vafaei, A., &; Navabi, Z. (2018). Near-Optimal Node Selection Procedure for Aging Monitor Placement. 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).https://doi.org/10.1109/iolts.2018.8474120 
LibreCat: /record/29459
DOI: 10.1109/iolts.2018.8474120

Deshmukh, J., Kunz, W., Wunderlich, H.-J., &; Hellebrand, S. (2017). Special Session on Early Life Failures. In 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE.https://doi.org/10.1109/vts.2017.7928933 
LibreCat: /record/12973
DOI: 10.1109/vts.2017.7928933

Kampmann, M., &; Hellebrand, S. (2017). Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. 20th IEEE International Symposium on Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’17).https://doi.org/10.1109/ddecs.2017.7934564 
LibreCat: /record/10576
DOI: 10.1109/ddecs.2017.7934564

Jenihhin, M., Kamkin, A., Navabi, Z., &; Sadeghi-Kohan, S. (2017). Universal mitigation of NBTI-induced aging by design randomization. 2016 IEEE East-West Design &; Test Symposium (EWDTS).https://doi.org/10.1109/ewdts.2016.7807635 
LibreCat: /record/29463
DOI: 10.1109/ewdts.2016.7807635

Kampmann, M., &; Hellebrand, S. (2016). X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. In 25th IEEE Asian Test Symposium (ATS’16) (pp. 1–6). Hiroshima, Japan: IEEE.https://doi.org/10.1109/ats.2016.20 
LibreCat: /record/12975
DOI: 10.1109/ats.2016.20

Kampmann, M., A. Kochte, M., Schneider, E., Indlekofer, T., Hellebrand, S., &; Wunderlich, H.-J. (2015). Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In 24th IEEE Asian Test Symposium (ATS’15) (pp. 109–114). Mumbai, India: IEEE.https://doi.org/10.1109/ats.2015.26 
LibreCat: /record/12976
DOI: 10.1109/ats.2015.26