Jafarzadeh, Hanieh, et al. “Time and Space Optimized Storage-Based BIST under Multiple Voltages and Variations.” European Test Symposium, The Hague, Netherlands, May 20-24, 2024, IEEE, p. 6.
LibreCat: /record/52744

Jafarzadeh, Hanieh, et al. “Vmin Testing under Variations: Defect vs. Fault Coverage.” IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, IEEE, p. 6.
LibreCat: /record/52742

Hellebrand, Sybille, et al. “Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle.” International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, p. 1.
LibreCat: /record/52743

Wunderlich, Hans-Joachim, et al. “Robust Test of Small Delay Faults under  PVT-Variations.” International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, p. 1.
LibreCat: /record/52745

Sadeghi-Kohan, Somayeh, et al. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.”10.1109/dsn-w58399.2023.00056__2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023, doi:10.1109/dsn-w58399.2023.00056.
LibreCat: /record/46739
DOI: 10.1109/dsn-w58399.2023.00056

Sadeghi-Kohan, Somayeh, et al. “Optimizing the Streaming of Sensor Data with Approximate Communication.” IEEE Asian Test Symposium (ATS’23), October 2023, 2023.
LibreCat: /record/46738

Jafarzadeh, Hanieh, et al. “Robust Pattern Generation for Small Delay Faults under Process Variations.” IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, 2023.
LibreCat: /record/45830

Sprenger, Alexander, et al. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, 2020.
LibreCat: /record/19422

Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects.”10.1109/vts48691.2020.9107591__38th IEEE VLSI Test Symposium (VTS), IEEE, 2020, doi:10.1109/vts48691.2020.9107591.
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DOI: 10.1109/vts48691.2020.9107591

Holst, Stefan, et al. “Logic Fault Diagnosis of Hidden Delay Defects.” IEEE International Test Conference (ITC’20), November 2020, 2020.
LibreCat: /record/19421

Maaz, Mohammad Urf, et al. “A Hybrid Space Compactor for Adaptive X-Handling.” 50th IEEE International Test Conference (ITC), IEEE, 2019, pp. 1–8.
LibreCat: /record/12918

Rezaeizadeh Rookerd, Ramin, et al. “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture.”10.1145/3194554.3194599__Proceedings of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018, doi:10.1145/3194554.3194599.
LibreCat: /record/29460
DOI: 10.1145/3194554.3194599

Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test.”10.1109/ddecs.2018.00020__2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &; Systems (DDECS), IEEE, 2018, doi:10.1109/ddecs.2018.00020.
LibreCat: /record/4575
DOI: 10.1109/ddecs.2018.00020

Liu, Chang, et al. “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention.”10.1109/ats.2018.00028__27th IEEE Asian Test Symposium (ATS’18), 2018, doi:10.1109/ats.2018.00028.
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DOI: 10.1109/ats.2018.00028

Sadeghi-Kohan, Somayeh, et al. “Near-Optimal Node Selection Procedure for Aging Monitor Placement.”10.1109/iolts.2018.8474120__2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018, doi:10.1109/iolts.2018.8474120.
LibreCat: /record/29459
DOI: 10.1109/iolts.2018.8474120

Deshmukh, Jyotirmoy, et al. “Special Session on Early Life Failures.”10.1109/vts.2017.7928933__35th IEEE VLSI Test Symposium (VTS’17), IEEE, 2017, doi:10.1109/vts.2017.7928933.
LibreCat: /record/12973
DOI: 10.1109/vts.2017.7928933

Kampmann, Matthias, and Sybille Hellebrand. “Design-for-FAST: Supporting X-Tolerant Compaction during Faster-than-at-Speed Test.”10.1109/ddecs.2017.7934564__20th IEEE International Symposium on Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’17), IEEE, 2017, doi:10.1109/ddecs.2017.7934564.
LibreCat: /record/10576
DOI: 10.1109/ddecs.2017.7934564

Jenihhin, Maksim, et al. “Universal Mitigation of NBTI-Induced Aging by Design Randomization.”10.1109/ewdts.2016.7807635__2016 IEEE East-West Design &; Test Symposium (EWDTS), IEEE, 2017, doi:10.1109/ewdts.2016.7807635.
LibreCat: /record/29463
DOI: 10.1109/ewdts.2016.7807635

Kampmann, Matthias, and Sybille Hellebrand. “X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test.”10.1109/ats.2016.20__25th IEEE Asian Test Symposium (ATS’16), IEEE, 2016, pp. 1–6, doi:10.1109/ats.2016.20.
LibreCat: /record/12975
DOI: 10.1109/ats.2016.20

Kampmann, Matthias, et al. “Optimized Selection of Frequencies for Faster-Than-at-Speed Test.”10.1109/ats.2015.26__24th IEEE Asian Test Symposium (ATS’15), IEEE, 2015, pp. 109–14, doi:10.1109/ats.2015.26.
LibreCat: /record/12976
DOI: 10.1109/ats.2015.26