Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. In: European Test Symposium, The Hague, Netherlands, May 20-24, 2024. IEEE; :6.

Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Vmin Testing under Variations: Defect vs. Fault Coverage. In: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024. IEEE; :6.

Hellebrand S, Sadeghi-Kohan S, Wunderlich H-J. Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. In: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.

Wunderlich H-J, Jafarzadeh H, Hellebrand S. Robust Test of Small Delay Faults under  PVT-Variations. In: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.

Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. In: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). IEEE; 2023. doi:10.1109/dsn-w58399.2023.00056

Sadeghi-Kohan S, Reimer JD, Hellebrand S, Wunderlich H-J. Optimizing the Streaming of Sensor Data with Approximate Communication. In: IEEE Asian Test Symposium (ATS’23), October 2023. ; 2023.

Jafarzadeh H, Klemme F, Reimer JD, et al. Robust Pattern Generation for Small Delay Faults under Process Variations. In: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE; 2023.

Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020. ; 2020.

Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. In: 38th IEEE VLSI Test Symposium (VTS). IEEE; 2020. doi:10.1109/vts48691.2020.9107591

Holst S, Kampmann M, Sprenger A, et al. Logic Fault Diagnosis of Hidden Delay Defects. In: IEEE International Test Conference (ITC’20), November 2020. ; 2020.

Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Adaptive X-Handling. In: 50th IEEE International Test Conference (ITC). IEEE; 2019:1-8.

Rezaeizadeh Rookerd R, Sadeghi-Kohan S, Navabi Z. Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. In: Proceedings of the 2018 on Great Lakes Symposium on VLSI. ACM; 2018. doi:10.1145/3194554.3194599

Sprenger A, Hellebrand S. Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. In: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &; Systems (DDECS). IEEE; 2018. doi:10.1109/ddecs.2018.00020

Liu C, Schneider E, Kampmann M, Hellebrand S, Wunderlich H-J. Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. In: 27th IEEE Asian Test Symposium (ATS’18). ; 2018. doi:10.1109/ats.2018.00028

Sadeghi-Kohan S, Vafaei A, Navabi Z. Near-Optimal Node Selection Procedure for Aging Monitor Placement. In: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). IEEE; 2018. doi:10.1109/iolts.2018.8474120

Deshmukh J, Kunz W, Wunderlich H-J, Hellebrand S. Special Session on Early Life Failures. In: 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE; 2017. doi:10.1109/vts.2017.7928933

Kampmann M, Hellebrand S. Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. In: 20th IEEE International Symposium on Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’17). IEEE; 2017. doi:10.1109/ddecs.2017.7934564

Jenihhin M, Kamkin A, Navabi Z, Sadeghi-Kohan S. Universal mitigation of NBTI-induced aging by design randomization. In: 2016 IEEE East-West Design &; Test Symposium (EWDTS). IEEE; 2017. doi:10.1109/ewdts.2016.7807635

Kampmann M, Hellebrand S. X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. In: 25th IEEE Asian Test Symposium (ATS’16). Hiroshima, Japan: IEEE; 2016:1-6. doi:10.1109/ats.2016.20

Kampmann M, A. Kochte M, Schneider E, Indlekofer T, Hellebrand S, Wunderlich H-J. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In: 24th IEEE Asian Test Symposium (ATS’15). Mumbai, India: IEEE; 2015:109-114. doi:10.1109/ats.2015.26