L. Clausing and M. Platzner, “ReconO: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support,”10.1109/ipdpsw55747.2022.00029__in 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW),10.1109/ipdpsw55747.2022.00029__Lyon, France, 2022, pp. 120–127, doi:10.1109/ipdpsw55747.2022.00029 .
LibreCat: /record/32855
DOI: 10.1109/ipdpsw55747.2022.00029

T. Hansmeier, M. Brede, and M. Platzner, “XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion,”10.1145/3520304.3533977__in GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Boston, MA, USA, 2022, pp. 2071–2079, doi:10.1145/3520304.3533977 .
LibreCat: /record/33253
DOI: 10.1145/3520304.3533977

C. Lienen and M. Platzner, “ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications.” 2022.
LibreCat: /record/29541

C. Lienen and M. Platzner, “Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS,” presented at the 2022 Sixth IEEE International Conference on Robotic Computing (IRC) , Neaples, Italy.
LibreCat: /record/34007

C. Lienen and M. Platzner, “Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications,”10.1109/DSD57027.2022.00088__presented at the 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Gran Canaria, Spain, doi:10.1109/DSD57027.2022.00088 .
LibreCat: /record/34005
DOI: 10.1109/DSD57027.2022.00088

Q. A. Ahmed and M. Platzner, “On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs,” presented at the IEEE Computer Society Annual Symposium on VLSI Aliathon Resort, Pafos, Cyprus, 2022.
LibreCat: /record/32342

M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis,” in Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, Virtual, 2021, pp. 27–32.
LibreCat: /record/21610
DOI: https://doi.org/10.1145/3453688.3461506

M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate Accelerators,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Tampa, Florida USA (Virtual), 2021, pp. 384–389.
LibreCat: /record/22309

L. M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, and M. Platzner, “Timing Optimization for Virtual FPGA Configurations,”10.1007/978-3-030-79025-7_4__in Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Virtual conference, doi:10.1007/978-3-030-79025-7_4 .
LibreCat: /record/21953
DOI: 10.1007/978-3-030-79025-7_4

T. Hansmeier, “Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS,”10.1145/3468044.3468055__presented at the International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), Online, 2021, doi:10.1145/3468044.3468055 .
LibreCat: /record/29137
DOI: 10.1145/3468044.3468055

C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,” arXiv:2107.07208. 2021.
LibreCat: /record/22764

T. Hansmeier and M. Platzner, “An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS,”10.1145/3449726.3463159__in GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Lille, France, 2021, pp. 1639–1647, doi:10.1145/3449726.3463159 .
LibreCat: /record/21813
DOI: 10.1145/3449726.3463159

Q. A. Ahmed, “Hardware Trojans in Reconfigurable Computing,”10.1109/vlsi-soc53125.2021.9606974__2021, doi:10.1109/vlsi-soc53125.2021.9606974 .
LibreCat: /record/29138
DOI: 10.1109/vlsi-soc53125.2021.9606974

Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing Bitstream-level Verification for FPGAs,”10.23919/DATE51398.2021.9474026__presented at the Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France, 2021, doi:10.23919/DATE51398.2021.9474026 .
LibreCat: /record/20681
DOI: 10.23919/DATE51398.2021.9474026

L. Clausing, “ReconO: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip,”10.1145/3468044.3468056__2021, doi:10.1145/3468044.3468056 .
LibreCat: /record/30909
DOI: 10.1145/3468044.3468056

H. Ghasemzadeh Mohammadi et al., “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics,”https://doi.org/10.1007/978-3-030-93736-2_27__2021, doi:https://doi.org/10.1007/978-3-030-93736-2_27 .
LibreCat: /record/30908
DOI: https://doi.org/10.1007/978-3-030-93736-2_27

Z.  Guetttatfi, P. Kaufmann, and M. Platzner, “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices,” in Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.
LibreCat: /record/3583

C. P. Gatica and M. Platzner, “Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures,” in Machine Learning for Cyber Physical Systems (ML4CPS 2017), 2020.
LibreCat: /record/21584
DOI: 10.1007/978-3-662-59084-3_9

L. M. Witschen, T. Wiersema, and M. Platzner, “Search Space Characterization for AxC Synthesis,” Fifth Workshop on Approximate Computing (AxC 2020). .
LibreCat: /record/20748

C. Lienen, M. Platzner, and B. Rinner, “ReconROS: Flexible Hardware Acceleration for RO Applications,” in Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.
LibreCat: /record/20750