Kaufmann P, Ho N, Platzner M. Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches. In: Adaptive Hardware and Systems (AHS). IEEE; 2017. doi:10.1109/AHS.2017.8046380
LibreCat: /record/10761
DOI: 10.1109/AHS.2017.8046380

Kaufmann P, Kalkreuth R. An Empirical Study on the Parametrization of Cartesian Genetic Programming. In: Genetic and Evolutionary Computation (GECCO), Compendium. ACM; 2017. doi:10.1145/3067695.3075980
LibreCat: /record/10762
DOI: 10.1145/3067695.3075980

Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness as design approach for visual sensor nodes. In: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). ; 2017:1-8. doi:10.1109/ReCoSoC.2017.8016147
LibreCat: /record/10780
DOI: 10.1109/ReCoSoC.2017.8016147

Ghribi I, Abdallah RB, Khalgui M, Platzner M. I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems. In: Communications in Computer and Information Science. Cham: Springer ; 2017. doi:10.1007/978-3-319-62569-0_8
LibreCat: /record/14893
DOI: 10.1007/978-3-319-62569-0_8

Boschmann A, Agne A, Witschen L, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312
LibreCat: /record/5812
DOI: 10.1109/reconfig.2015.7393312

Anwer J, Platzner M. Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs. In: Euromicro Conference on Digital System Design (DSD). ; 2016. doi:10.1109/DSD.2016.35
LibreCat: /record/10622
DOI: 10.1109/DSD.2016.35

Boschmann A, Dosen S, Werner A, Raies A, Farina D. A novel immersive augmented reality system for prosthesis training and assessment. In: Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI). ; 2016.
LibreCat: /record/10631

Meisner S, Platzner M. Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On. ReConFig. ; 2016:1-8. doi:10.1109/ReConFig.2016.7857193
LibreCat: /record/10712
DOI: 10.1109/ReConFig.2016.7857193

Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In: Proceedings of the 30th European Simulation and Modelling Conference (ESM). ; 2016.
LibreCat: /record/10766

Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Co-design Methodology for Real-time Embedded Systems. In: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA). ; 2016:185-195.
LibreCat: /record/10768

Boschmann A, Agne A, Witschen LM, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312
LibreCat: /record/15873
DOI: 10.1109/reconfig.2015.7393312

Graf T, Platzner M. Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In: Computer and Games. ; 2016.
LibreCat: /record/13151

Graf T, Platzner M. Monte-Carlo Simulation Balancing Revisited. In: IEEE Computational Intelligence and Games. ; 2016.
LibreCat: /record/13152

Wiersema T, Platzner M. Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016). ; 2016:1--8. doi:10.1109/ReCoSoC.2016.7533910
LibreCat: /record/132
DOI: 10.1109/ReCoSoC.2016.7533910

Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation &; Test in Europe Conference &; Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.
LibreCat: /record/168

Wiersema T, Wu S, Platzner M. On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In: Proceedings of the International Symposium in Reconfigurable Computing (ARC). LNCS. ; 2015:365--372. doi:10.1007/978-3-319-16214-0_32
LibreCat: /record/269
DOI: 10.1007/978-3-319-16214-0_32

Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178
LibreCat: /record/10673
DOI: 10.1109/AHS.2015.7231178

Kaufmann P, Shen C. Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In: Genetic and Evolutionary Computation (GECCO). ACM; 2015:409-416.
LibreCat: /record/10693

Meisner S, Platzner M. Comparison of thread signatures for error detection in hybrid multi-cores. In: Field Programmable Technology (FPT), 2015 International Conference On. FPT. ; 2015:212-215. doi:10.1109/FPT.2015.7393153
LibreCat: /record/10711
DOI: 10.1109/FPT.2015.7393153

H.W. Leong P, Amano H, Anderson J, et al. Significant papers from the first 25 years of the FPL conference. In: Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College; 2015:1-3. doi:10.1109/FPL.2015.7293747
LibreCat: /record/10765
DOI: 10.1109/FPL.2015.7293747