M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing,” presented at the IEEE Computer Society Annual Symposium on VLSI, Knoxville, Tennessee, USA, 2024.
LibreCat: /record/54468

Q. A. Ahmed, M. Awais, and M. Platzner, “MAAS: Hiding Trojans in Approximate Circuits,” presented at the The 24th International Symposium on Quality Electronic Design (ISQED’23), San Fransico CA 94023-0607, USA, 2023.
LibreCat: /record/44194

C. Lienen et al., “AutonomROS: A ReconROS-based Autonomous Driving Unit,”10.1109/irc59093.2023.00056__2023, doi:10.1109/irc59093.2023.00056 .
LibreCat: /record/53794
DOI: 10.1109/irc59093.2023.00056

L. Clausing, Z. Guetattfi, P. Kaufmann, C. Lienen, and M. Platzner, “On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconO,”https://doi.org/10.1007/978-3-031-42921-7_17__2023, doi:https://doi.org/10.1007/978-3-031-42921-7_17 .
LibreCat: /record/45913
DOI: https://doi.org/10.1007/978-3-031-42921-7_17

C. Lienen, A. P. Nowosad, and M. Platzner, “Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms,”https://doi.org/10.1145/3637843.3637846__doi:https://doi.org/10.1145/3637843.3637846 .
LibreCat: /record/46229
DOI: https://doi.org/10.1145/3637843.3637846

C. Lienen, S. H. Middeke, and M. Platzner, pgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications,”10.1109/IROS55552.2023.10341921__2023, doi:10.1109/IROS55552.2023.10341921 .
LibreCat: /record/43048
DOI: 10.1109/IROS55552.2023.10341921

F. Jentzsch, “Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML,”10.1109/fpl60245.2023.00066__2023, doi:10.1109/fpl60245.2023.00066 .
LibreCat: /record/53435
DOI: 10.1109/fpl60245.2023.00066

L. M. Witschen, T. Wiersema, L. D. Reuter, and M. Platzner, “Search Space Characterization for Approximate Logic Synthesis ,” presented at the 2022 59th ACM/IEEE Design Automation Conference (DAC), San Francisco, USA.
LibreCat: /record/29945

L. M. Witschen, T. Wiersema, M. Artmann, and M. Platzner, “MUSCAT: MUS-based Circuit Approximation Technique,” presented at the Design, Automation and Test in Europe (DATE), Online.
LibreCat: /record/29865

T. Hansmeier and M. Platzner, “Integrating Safety Guarantees into the Learning Classifier System XCS,”10.1007/978-3-031-02462-7_25__in Applications of Evolutionary Computation, EvoApplications 2022, Proceedings, Madrid, 2022, vol. 13224, pp. 386–401, doi:10.1007/978-3-031-02462-7_25 .
LibreCat: /record/30971
DOI: 10.1007/978-3-031-02462-7_25

L. Clausing and M. Platzner, “ReconO: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support,”10.1109/ipdpsw55747.2022.00029__in 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW),10.1109/ipdpsw55747.2022.00029__Lyon, France, 2022, pp. 120–127, doi:10.1109/ipdpsw55747.2022.00029 .
LibreCat: /record/32855
DOI: 10.1109/ipdpsw55747.2022.00029

T. Hansmeier, M. Brede, and M. Platzner, “XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion,”10.1145/3520304.3533977__in GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Boston, MA, USA, 2022, pp. 2071–2079, doi:10.1145/3520304.3533977 .
LibreCat: /record/33253
DOI: 10.1145/3520304.3533977

C. Lienen and M. Platzner, “ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications.” 2022.
LibreCat: /record/29541

C. Lienen and M. Platzner, “Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS,” presented at the 2022 Sixth IEEE International Conference on Robotic Computing (IRC) , Neaples, Italy.
LibreCat: /record/34007

C. Lienen and M. Platzner, “Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications,”10.1109/DSD57027.2022.00088__presented at the 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Gran Canaria, Spain, doi:10.1109/DSD57027.2022.00088 .
LibreCat: /record/34005
DOI: 10.1109/DSD57027.2022.00088

Q. A. Ahmed and M. Platzner, “On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs,” presented at the IEEE Computer Society Annual Symposium on VLSI Aliathon Resort, Pafos, Cyprus, 2022.
LibreCat: /record/32342

M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis,” in Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, Virtual, 2021, pp. 27–32.
LibreCat: /record/21610
DOI: https://doi.org/10.1145/3453688.3461506

M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate Accelerators,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Tampa, Florida USA (Virtual), 2021, pp. 384–389.
LibreCat: /record/22309

L. M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, and M. Platzner, “Timing Optimization for Virtual FPGA Configurations,”10.1007/978-3-030-79025-7_4__in Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Virtual conference, doi:10.1007/978-3-030-79025-7_4 .
LibreCat: /record/21953
DOI: 10.1007/978-3-030-79025-7_4

T. Hansmeier, “Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS,”10.1145/3468044.3468055__presented at the International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), Online, 2021, doi:10.1145/3468044.3468055 .
LibreCat: /record/29137
DOI: 10.1145/3468044.3468055