Walder, H., Steiger, C., &; Platzner, M. (2003). Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press.https://doi.org/10.1109/ipdps.2003.1213329 

Walder, H., &; Platzner, M. (2003). Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 284–287). CSREA Press.

Steiger, C., Walder, H., &; Platzner, M. (2003). Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL) (pp. 575–584). Berlin, Heidelberg: Springer.https://doi.org/10.1007/978-3-540-45234-8_56 

Steiger, C., Walder, H., Platzner, M., &; Thiele, L. (2003). Online scheduling and placement of real-time tasks to partially reconfigurable devices. In Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS) (pp. 252–235). IEEE CS Press.https://doi.org/10.1109/real.2003.1253269 

Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., &; Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In Proc. Int. Symp. on Wearable Computers (ISWC) (pp. 215–222). IEEE Computer Society.https://doi.org/10.1109/ISWC.2002.1167250 

Dyer, M., Plessl, C., &; Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2438, pp. 292–301). Springer.https://doi.org/10.1007/3-540-46117-5 

Plessl, C., &; Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) (pp. 163–172). IEEE Computer Society.https://doi.org/10.1109/FPGA.2002.1106671 

Walder, H., &; Platzner, M. (2002). Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 24–30). CSREA Press.

Plessl, C., &; Platzner, M. (2001). Instance-Specific Accelerators for Minimum Covering. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 85–91). CSREA Press.

Enzler, R., Platzner, M., Plessl, C., Thiele, L., &; Tröster, G. (2001). Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III (Vol. 4525, pp. 135–146).https://doi.org/10.1117/12.434376 

Eisenring, M. H., &; Platzner, M. (2000). An Implementation Framework for Run-time Reconfigurable Systems. In Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE) (pp. 151–157). CSREA Press.

Eisenring, M., &; Platzner, M. (2000). Optimization of Run-time Reconfigurable Embedded Systems. In Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL) (pp. 565–574). Springer.

Mencer, O., &; Platzner, M. (1999). Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press.https://doi.org/10.1109/hicss.1999.772883 

Eisenring, M., Platzner, M., &; Thiele, L. (1999). Communication Synthesis for Reconfigurable Embedded Systems. In Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL) (Vol. 1673, pp. 205–214). Springer.https://doi.org/10.1007/978-3-540-48302-1_21 

Platzner, M., &; De Micheli, G. (1998). Acceleration of satisfiability algorithms by reconfigurable hardware. In Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL)  (pp. 69–78). Berlin, Heidelberg: Springer .https://doi.org/10.1007/bfb0055234 

Platzner, M., &; Peters, L. (1997). Fast Signature Segmentation on a Multi-DSP Architecture. In Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing (Vol. 3166).

Röwekamp, T., Platzner, M., &; Peters, L. (1997). Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In Proceedings of the 8th International Conference on Signal Processing Applications &; Technology (ICSPAT) (pp. 829–833).

Lind, E., Platzner, M., &; Rinner, B. (1996). A Multi-DSP System with Dynamically Reconfigurable Processors. In Proceedings of the 7th International Conference on Signal Processing Applications &; Technology (ICSPAT).

Platzner, M., Rinner, B., &; Weiss, R. (1995). A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs. In Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing  (pp. 311–318). IEEE CS Press.

Brenner, E., Ginthör-Kalcsics, R., Hranitzky, R., Platzner, M., Rinner, B., Steger, C., &; Weiss, R. (1995). High-Performance Simulators Based on Multi-TM0. In Proceedings of the 5th Annual Texas Instruments TM0 Educators Conference.