Walder, Herbert, et al. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.”10.1109/ipdps.2003.1213329__Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003, doi:10.1109/ipdps.2003.1213329.

Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–87.

Steiger, Christoph, et al. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.”10.1007/978-3-540-45234-8_56__Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 575–84, doi:10.1007/978-3-540-45234-8_56.

Steiger, Christoph, et al. “Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices.”10.1109/real.2003.1253269__Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235, doi:10.1109/real.2003.1253269.

Plessl, Christian, et al. “Reconfigurable Hardware in Wearable Computing Nodes.”10.1109/ISWC.2002.1167250__Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–22, doi:10.1109/ISWC.2002.1167250.

Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.”10.1007/3-540-46117-5__Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2438, Springer, 2002, pp. 292–301, doi:10.1007/3-540-46117-5.

Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.”10.1109/FPGA.2002.1106671__Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–72, doi:10.1109/FPGA.2002.1106671.

Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.” Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002, pp. 24–30.

Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.

Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.”10.1117/12.434376__Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, vol. 4525, 2001, pp. 135–46, doi:10.1117/12.434376.

Eisenring, Michael H., and Marco Platzner. “An Implementation Framework for Run-Time Reconfigurable Systems.” Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), CSREA Press, 2000, pp. 151–57.

Eisenring, Michael, and Marco Platzner. “Optimization of Run-Time Reconfigurable Embedded Systems.” Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL), Springer, 2000, pp. 565–74.

Mencer, Oskar, and Marco Platzner. “Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment.”10.1109/hicss.1999.772883__Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32), IEEE CS Press, 1999, doi:10.1109/hicss.1999.772883.

Eisenring, Michael, et al. “Communication Synthesis for Reconfigurable Embedded Systems.”10.1007/978-3-540-48302-1_21__Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL), vol. 1673, Springer, 1999, pp. 205–14, doi:10.1007/978-3-540-48302-1_21.

Platzner, Marco, and Giovanni De Micheli. “Acceleration of Satisfiability Algorithms by Reconfigurable Hardware.”10.1007/bfb0055234__Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) , Springer , 1998, pp. 69–78, doi:10.1007/bfb0055234.

Platzner, Marco, and Liliane Peters. “Fast Signature Segmentation on a Multi-DSP Architecture.” Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing, vol. 3166, 1997.

Röwekamp, Thomas, et al. “Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP.” Proceedings of the 8th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1997, pp. 829–33.

Lind, Erich, et al. “A Multi-DSP System with Dynamically Reconfigurable Processors.” Proceedings of the 7th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1996.

Platzner, Marco, et al. “A Distributed Computer Architecture for Qualitative Simulation Based on a Multi-DSP and FPGAs.” Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing , IEEE CS Press, 1995, pp. 311–18.

Brenner, Eugen, et al. “High-Performance Simulators Based on Multi-TM0.” Proceedings of the 5th Annual Texas Instruments TM0 Educators Conference, 1995.