S. Redif and S. Kasap, “Parallel algorithm for computation of second-order sequential best rotations,” Int. Journal of Electronics, vol. 100, no. 12, pp. 1646–1651, 2012.
LibreCat: /record/2173
DOI: 10.1080/00207217.2012.751343

S. Kasap and K. Benkrid, “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer,” Journal of Computers, vol. 7, no. 6, pp. 1312–1328, 2012.
LibreCat: /record/2174

P. Kaufmann, K. Glette, M. Platzner, and J. Torresen, “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture,” International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), vol. 3, no. 4, pp. 17–31, 2012.
LibreCat: /record/10685
DOI: 10.4018/jaras.2012100102

T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,”10.1016/j.micpro.2011.04.002__Microprocessors and Microsystems, vol. 36, no. 2, pp. 110–126, 2012, doi:10.1016/j.micpro.2011.04.002 .
LibreCat: /record/2108
DOI: 10.1016/j.micpro.2011.04.002

M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,”10.1155/2012/418315__Int. Journal of Reconfigurable Computing (IJRC), 2012, doi:10.1155/2012/418315 .
LibreCat: /record/2177
DOI: 10.1155/2012/418315

T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study,”10.1155/2011/760954__Int. Journal of Recon- figurable Computing (IJRC), 2011, doi:10.1155/2011/760954 .
LibreCat: /record/2201
DOI: 10.1155/2011/760954

S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification,” International Journal of Reconfigurable Computing, vol. 2010, 2010.
LibreCat: /record/10605
DOI: 10.1155/2010/180242

U. Kebschull, M. Platzner, and J. Teich, “Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial),” IET Computers Digital Techniques, vol. 4, no. 3, pp. 157–158, 2010.
LibreCat: /record/10694
DOI: 10.1049/iet-cdt.2010.9044

E. Lübbers and M. Platzner, “ReconOS: Multithreaded Programming for Reconfigurable Computers,” ACM Transactions on Embedded Computing Systems, vol. 9, no. 1, pp. 8:1-8:33, 2009.
LibreCat: /record/10703
DOI: 10.1145/1596532.1596540

N. Bergmann, M. Platzner, and J. Teich, “Dynamically Reconfigurable Architectures (editorial),” EURASIP Journal on Embedded Systems, vol. 2007, pp. 1–2, 2007.
LibreCat: /record/10625
DOI: 10.1155/2007/28405

K. Danne, R. Mühlenbernd, and M. Platzner, “Server-based execution of periodic tasks on dynamically reconfigurable hardware,” IET Computers Digital Techniques, vol. 1, no. 4, pp. 295–302, 2007.
LibreCat: /record/10646
DOI: 10.1049/iet-cdt:20060186

R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” Microprocessors and Microsystems, vol. 29, no. 2–3, pp. 63–73, 2005.
LibreCat: /record/2412
DOI: 10.1016/j.micpro.2004.06.004

C. Steiger, H. Walder, and M. Platzner, “Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks,” IEEE Transactions on Computers, vol. 53, no. 11, pp. 1393–1407, 2004.
LibreCat: /record/10742
DOI: 10.1109/tc.2004.99

C. Plessl et al., “The Case for Reconfigurable Hardware in Wearable Computing,” Personal and Ubiquitous Computing, vol. 7, no. 5, pp. 299–308, 2003.
LibreCat: /record/2419
DOI: 10.1007/s00779-003-0243-x

C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” Journal of Supercomputing, vol. 26, no. 2, pp. 109–129, 2003.
LibreCat: /record/2420
DOI: 10.1023/a:1024443416592

M. Eisenring and M. Platzner, “A Framework for Run-time Reconfigurable Systems,” The Journal of Supercomputing, vol. 21, no. 2, pp. 145–159, 2002.
LibreCat: /record/10651
DOI: 10.1023/a:1013627403946

O. Mencer, M. Platzner, M. Morf, and M. J. Flynn, “Object-oriented domain specific compilers for programming FPGAs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 1, pp. 205–210, 2001.
LibreCat: /record/10713
DOI: 10.1109/92.920835

M. Platzner, “Reconfigurable accelerators for combinatorial problems,” Computer, vol. 33, no. 4, pp. 58–60, 2000.
LibreCat: /record/6507
DOI: 10.1109/2.839322

M. Eisenring and M. Platzner, “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems,” IEE Proceedings -- Computers &; Digital Techniques, vol. 147, pp. 159–165, 2000.
LibreCat: /record/10606
DOI: 10.1049/ip-cdt:20000496

M. Platzner, B. Rinner, and R. Weiss, “Toward embedded qualitative simulation: a specialized computer architecture for QSim,” IEEE Intelligent Systems, vol. 15, no. 2, pp. 62–68, 2000.
LibreCat: /record/10725
DOI: 10.1109/5254.850829