Server-based execution of periodic tasks on dynamically reconfigurable hardware
K. Danne, R. Mühlenbernd, M. Platzner, IET Computers Digital Techniques 1 (2007) 295–302.
LibreCat: /record/10646
DOI: 10.1049/iet-cdt:20060186

System-level performance evaluation of reconfigurable processors
R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73.
LibreCat: /record/2412
DOI: 10.1016/j.micpro.2004.06.004

Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks
C. Steiger, H. Walder, M. Platzner, IEEE Transactions on Computers 53 (2004) 1393–1407.
LibreCat: /record/10742
DOI: 10.1109/tc.2004.99

The Case for Reconfigurable Hardware in Wearable Computing
C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, G. Tröster, Personal and Ubiquitous Computing 7 (2003) 299–308.
LibreCat: /record/2419
DOI: 10.1007/s00779-003-0243-x

Instance-Specific Accelerators for Minimum Covering
C. Plessl, M. Platzner, Journal of Supercomputing 26 (2003) 109–129.
LibreCat: /record/2420
DOI: 10.1023/a:1024443416592

A Framework for Run-time Reconfigurable Systems
M. Eisenring, M. Platzner, The Journal of Supercomputing 21 (2002) 145–159.
LibreCat: /record/10651
DOI: 10.1023/a:1013627403946

Object-oriented domain specific compilers for programming FPGAs
O. Mencer, M. Platzner, M. Morf, M. J. Flynn, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (2001) 205–210.
LibreCat: /record/10713
DOI: 10.1109/92.920835

Reconfigurable accelerators for combinatorial problems
M. Platzner, Computer 33 (2000) 58–60.
LibreCat: /record/6507
DOI: 10.1109/2.839322

Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems
M. Eisenring, M. Platzner, IEE Proceedings -- Computers &; Digital Techniques 147 (2000) 159–165.
LibreCat: /record/10606
DOI: 10.1049/ip-cdt:20000496

Toward embedded qualitative simulation: a specialized computer architecture for QSim
M. Platzner, B. Rinner, R. Weiss, IEEE Intelligent Systems 15 (2000) 62–68.
LibreCat: /record/10725
DOI: 10.1109/5254.850829

Reconfigurable Computer Architectures
M. Platzner, E&;i Elektrotechnik Und Informationstechnik 115 (1998) 143–148.
LibreCat: /record/10607

Design and Implementation of a Parallel Constraint Satisfaction Algorithm
M. Platzner, B. Rinner, International Journal of Computers &; Their Applications 5 (1998) 106–116.
LibreCat: /record/10608

A Computer Architecture to Support Qualitative Simulation in Industrial Applications
M. Platzner, B. Rinner, R. Weiss, E &; i Elektrotechnik Und Informationstechnik 114 (1997) 13–18.
LibreCat: /record/10609

Parallel qualitative simulation
M. Platzner, B. Rinner, R. Weiss, Simulation Practice and Theory 5 (1997) 623–638.
LibreCat: /record/10724
DOI: 10.1016/s0928-4869(97)00008-6

Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation
M. Platzner, B. Rinner, R. Weiss, J.UCS Journal of Universal Computer Science 12 (1995) 811–820.
LibreCat: /record/10610

Erfahrungen mit einer Multi-Signalprozessorarchitektur (TM0)
M. Platzner, C. Steger, Mikroelektronik (1993).
LibreCat: /record/13466