Danne K, Mühlenbernd R, Platzner M. Server-based execution of periodic tasks on dynamically reconfigurable hardware. IET Computers Digital Techniques. 2007;1(4):295-302. doi:10.1049/iet-cdt:20060186
LibreCat: /record/10646
DOI: 10.1049/iet-cdt:20060186

Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems. 2005;29(2-3):63-73. doi:10.1016/j.micpro.2004.06.004
LibreCat: /record/2412
DOI: 10.1016/j.micpro.2004.06.004

Steiger C, Walder H, Platzner M. Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. IEEE Transactions on Computers. 2004;53(11):1393-1407. doi:10.1109/tc.2004.99
LibreCat: /record/10742
DOI: 10.1109/tc.2004.99

Plessl C, Enzler R, Walder H, et al. The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing. 2003;7(5):299-308. doi:10.1007/s00779-003-0243-x
LibreCat: /record/2419
DOI: 10.1007/s00779-003-0243-x

Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing. 2003;26(2):109-129. doi:10.1023/a:1024443416592
LibreCat: /record/2420
DOI: 10.1023/a:1024443416592

Eisenring M, Platzner M. A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing. 2002;21(2):145-159. doi:10.1023/a:1013627403946
LibreCat: /record/10651
DOI: 10.1023/a:1013627403946

Mencer O, Platzner M, Morf M, J. Flynn M. Object-oriented domain specific compilers for programming FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2001;9(1):205-210. doi:10.1109/92.920835
LibreCat: /record/10713
DOI: 10.1109/92.920835

Platzner M. Reconfigurable accelerators for combinatorial problems. Computer. 2000;33(4):58-60. doi:10.1109/2.839322
LibreCat: /record/6507
DOI: 10.1109/2.839322

Eisenring M, Platzner M. Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. IEE Proceedings -- Computers &; Digital Techniques. 2000;147:159-165. doi:10.1049/ip-cdt:20000496
LibreCat: /record/10606
DOI: 10.1049/ip-cdt:20000496

Platzner M, Rinner B, Weiss R. Toward embedded qualitative simulation: a specialized computer architecture for QSim. IEEE Intelligent Systems. 2000;15(2):62-68. doi:10.1109/5254.850829
LibreCat: /record/10725
DOI: 10.1109/5254.850829

Platzner M. Reconfigurable Computer Architectures. e&;i Elektrotechnik und Informationstechnik. 1998;115:143-148.
LibreCat: /record/10607

Platzner M, Rinner B. Design and Implementation of a Parallel Constraint Satisfaction Algorithm. International Journal of Computers &; Their Applications. 1998;5:106-116.
LibreCat: /record/10608

Platzner M, Rinner B, Weiss R. A Computer Architecture to Support Qualitative Simulation in Industrial Applications. e &; i Elektrotechnik und Informationstechnik. 1997;114:13-18.
LibreCat: /record/10609

Platzner M, Rinner B, Weiss R. Parallel qualitative simulation. Simulation Practice and Theory. 1997;5(7-8):623-638. doi:10.1016/s0928-4869(97)00008-6
LibreCat: /record/10724
DOI: 10.1016/s0928-4869(97)00008-6

Platzner M, Rinner B, Weiss R. Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation. JUCS Journal of Universal Computer Science. 1995;12:811-820.
LibreCat: /record/10610

Platzner M, Steger C. Erfahrungen mit einer Multi-Signalprozessorarchitektur (TM0). Mikroelektronik. 1993.
LibreCat: /record/13466