K. Danne, R. Mühlenbernd, and M. Platzner, “Server-based execution of periodic tasks on dynamically reconfigurable hardware,” IET Computers Digital Techniques, vol. 1, no. 4, pp. 295–302, 2007.
LibreCat: /record/10646
DOI: 10.1049/iet-cdt:20060186

R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” Microprocessors and Microsystems, vol. 29, no. 2–3, pp. 63–73, 2005.
LibreCat: /record/2412
DOI: 10.1016/j.micpro.2004.06.004

C. Steiger, H. Walder, and M. Platzner, “Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks,” IEEE Transactions on Computers, vol. 53, no. 11, pp. 1393–1407, 2004.
LibreCat: /record/10742
DOI: 10.1109/tc.2004.99

C. Plessl et al., “The Case for Reconfigurable Hardware in Wearable Computing,” Personal and Ubiquitous Computing, vol. 7, no. 5, pp. 299–308, 2003.
LibreCat: /record/2419
DOI: 10.1007/s00779-003-0243-x

C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” Journal of Supercomputing, vol. 26, no. 2, pp. 109–129, 2003.
LibreCat: /record/2420
DOI: 10.1023/a:1024443416592

M. Eisenring and M. Platzner, “A Framework for Run-time Reconfigurable Systems,” The Journal of Supercomputing, vol. 21, no. 2, pp. 145–159, 2002.
LibreCat: /record/10651
DOI: 10.1023/a:1013627403946

O. Mencer, M. Platzner, M. Morf, and M. J. Flynn, “Object-oriented domain specific compilers for programming FPGAs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 1, pp. 205–210, 2001.
LibreCat: /record/10713
DOI: 10.1109/92.920835

M. Platzner, “Reconfigurable accelerators for combinatorial problems,” Computer, vol. 33, no. 4, pp. 58–60, 2000.
LibreCat: /record/6507
DOI: 10.1109/2.839322

M. Eisenring and M. Platzner, “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems,” IEE Proceedings -- Computers &; Digital Techniques, vol. 147, pp. 159–165, 2000.
LibreCat: /record/10606
DOI: 10.1049/ip-cdt:20000496

M. Platzner, B. Rinner, and R. Weiss, “Toward embedded qualitative simulation: a specialized computer architecture for QSim,” IEEE Intelligent Systems, vol. 15, no. 2, pp. 62–68, 2000.
LibreCat: /record/10725
DOI: 10.1109/5254.850829

M. Platzner, “Reconfigurable Computer Architectures,” e&;i Elektrotechnik und Informationstechnik, vol. 115, pp. 143–148, 1998.
LibreCat: /record/10607

M. Platzner and B. Rinner, “Design and Implementation of a Parallel Constraint Satisfaction Algorithm,” International Journal of Computers &; Their Applications, vol. 5, pp. 106–116, 1998.
LibreCat: /record/10608

M. Platzner, B. Rinner, and R. Weiss, “A Computer Architecture to Support Qualitative Simulation in Industrial Applications,” e &; i Elektrotechnik und Informationstechnik, vol. 114, pp. 13–18, 1997.
LibreCat: /record/10609

M. Platzner, B. Rinner, and R. Weiss, “Parallel qualitative simulation,” Simulation Practice and Theory, vol. 5, no. 7–8, pp. 623–638, 1997.
LibreCat: /record/10724
DOI: 10.1016/s0928-4869(97)00008-6

M. Platzner, B. Rinner, and R. Weiss, “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation,” J.UCS Journal of Universal Computer Science, vol. 12, pp. 811–820, 1995.
LibreCat: /record/10610

M. Platzner and C. Steger, “Erfahrungen mit einer Multi-Signalprozessorarchitektur (TM0),” Mikroelektronik, 1993.
LibreCat: /record/13466