Q. A. Ahmed, T. Wiersema, and M. Platzner, “Post-configuration Activation of Hardware Trojans in FPGAs,”10.1007/s41635-024-00147-5__Journal of Hardware and Systems Security, 2024, doi:10.1007/s41635-024-00147-5 .

F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, and M. Platzner, “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures,”10.1109/MM.2022.3202091__IEEE Micro, vol. 42, no. 6, pp. 125–133, 2022, doi:10.1109/MM.2022.3202091 .

C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,”10.1145/3494571__ACM Transactions on Reconfigurable Technology and Systems, pp. 1–20, 2021, doi:10.1145/3494571 .

A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, and S. Dosen, “Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis,”10.1186/s12984-021-00822-6__Journal of NeuroEngineering and Rehabilitation, vol. 18, no. 1, Art. no. 25, 2021, doi:10.1186/s12984-021-00822-6 .

A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,”10.1109/tc.2021.3107196__IEEE Transactions on Computers, pp. 1–1, 2021, doi:10.1109/tc.2021.3107196 .

M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware Co-Verification for Custom Instruction Set Processors,”10.1109/ACCESS.2021.3131213__IEEE Access, 2021, doi:10.1109/ACCESS.2021.3131213 .

L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, pp. 2084–2088, 2020.

N. Ho, P. Kaufmann, and M. Platzner, “Evolution of Application-Specific Cache Mappings,” International Journal of Hybrid intelligent Systems, 2020.

J. Anwer, S. Meisner, and M. Platzner, “Dynamic Reliability Management for FPGA-Based Systems,” International Journal of Reconfigurable Computing, pp. 1–19, 2020.

K. Bellman et al., “Self-aware Cyber-Physical Systems,” ACM Transactions on Cyber-Physical Systems, vol. Accepted for Publication, pp. 1–24, 2020.

L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Microelectronics Reliability, vol. 99, pp. 277–290, 2019.

A. Boschmann, A. Agne, G. Thombansen, L. M. Witschen, F. Kraus, and M. Platzner, “Zynq-based acceleration of robust high density myoelectric signal processing,” Journal of Parallel and Distributed Computing, vol. 123, pp. 77–89, 2019.

T. Hansmeier, M. Platzner, M. J. H. Pantho, and D. Andrews, “An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology,” Journal of Signal Processing Systems, vol. 91, no. 11, pp. 1259–1272, 2019.

M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,”10.1007/s00287-019-01187-w__Informatik Spektrum, 2019, doi:10.1007/s00287-019-01187-w .

I. Ghribi, R. B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, and M. Platzner, “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints,” IEEE Access, pp. 14078–14092, 2018.

C. Shen, P. Kaufmann, and M. Braun, “Three-Stage Power System Restoration Methodology Considering Renewable Energies,” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), vol. 94, pp. 287–299, 2017.

T. Isenberg, M. Platzner, H. Wehrheim, and T. Wiersema, “Proof-Carrying Hardware via Inductive Invariants,” ACM Transactions on Design Automation of Electronic Systems, no. 4, pp. 61:1--61:23, 2017.

P. H.W. Leong et al., “The First 25 Years of the FPL Conference – Significant Papers,” ACM Transactions on Reconfigurable Technology and Systems, 2017.

R. F. DeMara, M. Platzner, and M. Ottavi, “Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial),” IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing, 2017.

J. Anwer and M. Platzner, “Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus,” Microprocessors and Microsystems, pp. 160–172, 2017.