A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, Stuttgart, DE, 2020.
LibreCat: /record/24027

RISC-V Extensions for Bit Manipulation Instructions
B. Koppelmann, P. Adelt, W. Müller, C. Scheytt, in: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Rhodos, Griechenland, 2019.
LibreCat: /record/24058
DOI: 10.1109/PATMOS.2019.8862170

Analyse sicherheitskritischer Software fur RISC-V Prozessoren
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019), Kaiserslautern, DE, 2019.
LibreCat: /record/24060

QEMU for Dynamic Memory Analysis of Security Sensitive Software
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, B. Driessen, in:  2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, Florence, Italy, 2019, pp. 32–34.
LibreCat: /record/24061

QEMU Support for RISC-V: Current State and Future Releases
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, 2nd International Workshop on RISC-V Research Activities (Presentation) (2019).
LibreCat: /record/24063

Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT
O. Bringmann, W. Ecker, W. Müller, D. Müller-Gridschneder, eds., Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT, Florence, Italy, 2019.
LibreCat: /record/53596

Current and Future RISC-V Activities for Virtual Prototyping and Chip Design
P. Adelt, B. Koppelmann, W. Müller, International Workshop on RISC-V Research Activities Presentation (2018).
LibreCat: /record/24194

Analog fault simulation automation at schematic level with random sampling techniques
L. Wu, M.K. Hussain, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2018 13th International Conference on Design &; Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, Italy/Taormina, 2018.
LibreCat: /record/24196
DOI: 10.1109/DTIS.2018.8368549

Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT
O. Bringmann, W. Ecker, W. Müller, D. Müller-Gridschneder, eds., Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT, Dresden, Germany, 2018.
LibreCat: /record/53595

Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen
P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, C. Scheytt, in: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Germany, Paderborn, 2017.
LibreCat: /record/24220
DOI: 10.17619/UNIPB/1-93

SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study
L. Wu, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), Lausanne, Switzerland, 2017, p. 68.
LibreCat: /record/24223

ANALISA - A Tool for Static Instruction Set Analysis
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation, Lausanne, CH, 2017.
LibreCat: /record/24224

An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , Lausanne, Switzerland, 2017, p. 44.
LibreCat: /record/24225

Fast Dynamic Fault Injection for Virtual Microcontroller Platforms
P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, C. Scheytt, in: Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC), Tallin, Estonia, 2016.
LibreCat: /record/24264
DOI: 10.1109/VLSI-SoC.2016.7753545

Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study
S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, C. Novello, in: Analog 2016 - VDE, 2016.
LibreCat: /record/24263

On the Correlation of HW Faults and SW Errors
W. Müller, L. Wu, C. Scheytt, M. Becker, S. Schoenberg, in: D. Mueller-Gritschneder, W. Müller, S. Mitra (Eds.), Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), Amsterdam, Netherland, 2015.
LibreCat: /record/24289

Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems
D. Müller-Gridschneder, W. Müller, S. Mitra, eds., Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems, Amsterdam, Netherlands, 2015.
LibreCat: /record/53590

Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System Software
M. Becker, C. Kuznik, W. Müller, in: 17th Euromicro Conference on Digital Systems Design (DSD), 2014.
LibreCat: /record/25145

Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems
M. Becker, C. Kuznik, W. Müller, in: ACM/IEEE 5th International Conference on Cyber-Physical Systems, 2014.
LibreCat: /record/25155

Portierung der TriCore-Architektur auf QEMU
B. Koppelmann, M. Becker, W. Müller, in: 17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) , 2014.
LibreCat: /record/25161