Hellebrand, S. (1999). Selbsttestbare Steuerwerke - Strukturen und Syntheseverfahren. Verlag Dr. Kovac, Hamburg: Verlag Dr. Kovac, Hamburg.
LibreCat: /record/13065

Hellebrand, S., Wunderlich, H.-J., &; N. Yarmolik, V. (1999). Exploiting Symmetries to Speed Up Transparent BIST. 11th GI/ITG/GMM/IEEE Workshop.
LibreCat: /record/13093

Hellebrand, S., Wunderlich, H.-J., A. Ivaniuk, A., V. Klimets, Y., &; N. Yarmolik, V. (1999). Error Detecting Refreshment for Embedded DRAMs. 17th IEEE VLSI Test Symposium (VTS’99), 384–390.https://doi.org/10.1109/vtest.1999.766693 
LibreCat: /record/13006
DOI: 10.1109/vtest.1999.766693

N. Yarmolik, V., V. Bykov, I., Hellebrand, S., &; Wunderlich, H.-J. (1999). Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. Third European Dependable Computing Conference (EDCC-3).
LibreCat: /record/13066

Hellebrand, S., Wunderlich, H.-J., &; N. Yarmolik, V. (1999). Symmetric Transparent BIST for RAMs. Design Automation and Test in Europe (DATE’99), 702–707.
LibreCat: /record/13067

Hellebrand, S., &; Wunderlich, H.-J. (1998). Test und Synthese schneller eingebetteter Systeme. Universität Stuttgart.
LibreCat: /record/13029

N. Yarmolik, V., Hellebrand, S., &; Wunderlich, H.-J. (1998). Efficient Consistency Checking for Embedded Memories. 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.
LibreCat: /record/13091

N. Yarmolik, V., Hellebrand, S., &; Wunderlich, H.-J. (1998). Efficient Consistency Checking for Embedded Memories. 10th GI/ITG/GMM/IEEE Workshop.
LibreCat: /record/13092

Hellebrand, S., Wunderlich, H.-J., &; Hertwig, A. (1998). Mixed-Mode BIST Using Embedded Processors. In Mixed-Mode BIST Using Embedded Processors. Kluwer Academic Publishers.
LibreCat: /record/13060

Hellebrand, S., Wunderlich, H.-J., &; Hertwig, A. (1998). Mixed-Mode BIST Using Embedded Processors. Journal of Electronic Testing Theory and Applications - JETTA, 12(1/2), 127–138.
LibreCat: /record/13061

Hellebrand, S., Hertwig, A., &; Wunderlich, H.-J. (1998). Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. IEEE Design and Test, 15(4), 36–41.
LibreCat: /record/13064

Hertwig, A., Hellebrand, S., &; Wunderlich, H.-J. (1998). Fast Self-Recovering Controllers. 16th IEEE VLSI Test Symposium (VTS’98), 296–302.https://doi.org/10.1109/vtest.1998.670883 
LibreCat: /record/13007
DOI: 10.1109/vtest.1998.670883

Hellebrand, S., Wunderlich, H.-J., &; N. Yarmolik, V. (1998). Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. Design Automation and Test in Europe (DATE’98), 173–179.https://doi.org/10.1109/date.1998.655853 
LibreCat: /record/13008
DOI: 10.1109/date.1998.655853

N. Yarmolik, V., V. Klimets, Y., Hellebrand, S., &; Wunderlich, H.-J. (1998). New Transparent RAM BIST Based on Self-Adjusting Output Data Compression. Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’98), 27–33.
LibreCat: /record/13063

Tsai, K.-H., Hellebrand, S., Rajski, J., &; Marek-Sadowska, M. (1997). STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.
LibreCat: /record/13089

Hertwig, A., Hellebrand, S., &; Wunderlich, H.-J. (1997). Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 3rd IEEE International On-Line Testing Workshop, Crete, Greece.
LibreCat: /record/13090

Tsai, K.-H., Hellebrand, S., Marek-Sadowska, M., &; Rajski, J. (1997). STARBIST: Scan Autocorrelated Random Pattern Generation. 34th ACM/IEEE Design Automation Conference (DAC’97).https://doi.org/10.1109/dac.1997.597194 
LibreCat: /record/13009
DOI: 10.1109/dac.1997.597194

Hellebrand, S., &; Wunderlich, H.-J. (1996). Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA.
LibreCat: /record/13087

Hellebrand, S., Wunderlich, H.-J., &; Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France.
LibreCat: /record/13088

Hellebrand, S., Wunderlich, H.-J., &; Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. IEEE International Test Conference (ITC’96), 195–204.https://doi.org/10.1109/test.1996.556962 
LibreCat: /record/13010
DOI: 10.1109/test.1996.556962