A. Cook, S. Hellebrand, and H.-J. Wunderlich, “Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test,” in 17th IEEE European Test Symposium (ETS’12), 2012, pp. 1–6.
LibreCat: /record/12981
DOI: 10.1109/ets.2012.6233025

A. Cook, S. Hellebrand, and H.-J. Wunderlich, Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern. 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany, 2012.
LibreCat: /record/13074

A. Cook, S. Hellebrand, T. Indlekofer, and H.-J. Wunderlich, “Diagnostic Test of Robust Circuits,” in 20th IEEE Asian Test Symposium (ATS’11), 2011, pp. 285–290.
LibreCat: /record/12982
DOI: 10.1109/ats.2011.55

I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, and P. Maxwell, “Towards Variation-Aware Test Methods,” in 16th IEEE European Test Symposium Trondheim (ETS’11), 2011.
LibreCat: /record/12984
DOI: 10.1109/ets.2011.51

A. Cook, S. Hellebrand, T. Indlekofer, and H.-J. Wunderlich, “Robuster Selbsttest mit Diagnose,” in 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit und Entwurf,” 2011, pp. 48–53.
LibreCat: /record/13053

F. Hopsch et al., “Variation-Aware Fault Modeling,” SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer, vol. 54, no. 4, pp. 1813–1826, 2011.
LibreCat: /record/13052

V. Fröse, R. Ibers, and S. Hellebrand, Testdatenkompression mit Hilfe der Netzwerkinfrastruktur. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
LibreCat: /record/10670

B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” in 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), 2010.
LibreCat: /record/12987
DOI: 10.1109/dsnw.2010.5542612

M. Hunger and S. Hellebrand, “Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 81–88.
LibreCat: /record/13051

S. Hellebrand, Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180, 2010.
LibreCat: /record/13073

F. Hopsch et al., “Variation-Aware Fault Modeling,”10.1109/ats.2010.24__in 19th IEEE Asian Test Symposium (ATS’10), 2010, pp. 87–93, doi:10.1109/ats.2010.24 .
LibreCat: /record/12983
DOI: 10.1109/ats.2010.24

T. Indlekofer, M. Schnittger, and S. Hellebrand, “Efficient Test Response Compaction for Robust BIST Using Parity Sequences,”10.1109/iccd.2010.5647648__in 28th IEEE International Conference on Computer Design (ICCD’10), 2010, pp. 480–485, doi:10.1109/iccd.2010.5647648 .
LibreCat: /record/12985
DOI: 10.1109/iccd.2010.5647648

M. Hunger and S. Hellebrand, “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems,”10.1109/dft.2010.19__in 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 2010, pp. 101–108, doi:10.1109/dft.2010.19 .
LibreCat: /record/12986
DOI: 10.1109/dft.2010.19

V. Froese, R. Ibers, and S. Hellebrand, “Reusing NoC-Infrastructure for Test Data Compression,”10.1109/vts.2010.5469570__in 28th IEEE VLSI Test Symposium (VTS’10), 2010, pp. 227–231, doi:10.1109/vts.2010.5469570 .
LibreCat: /record/12988
DOI: 10.1109/vts.2010.5469570

B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” 2010.
LibreCat: /record/13049

T. Indlekofer, M. Schnittger, and S. Hellebrand, “Robuster Selbsttest mit extremer Kompaktierung,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 17–24.
LibreCat: /record/13050

M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “ATPG-Based Grading of Strong Fault-Secureness,”10.1109/iolts.2009.5196027__2009, doi:10.1109/iolts.2009.5196027 .
LibreCat: /record/12991
DOI: 10.1109/iolts.2009.5196027

S. Hellebrand and M. Hunger, “Are Robust Circuits Really Robust?,”10.1109/dft.2009.28__in 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 2009, p. 77, doi:10.1109/dft.2009.28 .
LibreCat: /record/12990
DOI: 10.1109/dft.2009.28

M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung,” 2009.
LibreCat: /record/13030

T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, and C. G. Zoellin, Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008.
LibreCat: /record/13033