Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations
H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: European Test Symposium, The Hague, Netherlands, May 20-24, 2024, IEEE, n.d., p. 6.
LibreCat: /record/52744

Vmin Testing under Variations: Defect vs. Fault Coverage
H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, IEEE, n.d., p. 6.
LibreCat: /record/52742

Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle
S. Hellebrand, S. Sadeghi-Kohan, H.-J. Wunderlich, in: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.
LibreCat: /record/52743

Robust Test of Small Delay Faults under  PVT-Variations
H.-J. Wunderlich, H. Jafarzadeh, S. Hellebrand, in: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.
LibreCat: /record/52745

Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression
A. Stiballe, J.D. Reimer, S. Sadeghi-Kohan, S. Hellebrand, Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression, 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, Darmstadt, Germany, 2024.
LibreCat: /record/50284

Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks
M. Ustimova, S. Sadeghi-Kohan, S. Hellebrand, Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks, 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, Darmstadt, Germany, 2024.
LibreCat: /record/51799

On Cryptography Effects on Interconnect Reliability
A. Ghazal, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, On Cryptography Effects on Interconnect Reliability, 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, Erfurt, Germany, 2023.
LibreCat: /record/35204

Approximate Computing: Balancing Performance, Power, Reliability, and Safety
A. Badran, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: 28th IEEE European Test Symposium (ETS’23), May 2023, Venice, Italy, 2023.
LibreCat: /record/41875

Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, in: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023.
LibreCat: /record/46739
DOI: 10.1109/dsn-w58399.2023.00056

Optimizing the Streaming of Sensor Data with Approximate Communication
S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, in: IEEE Asian Test Symposium (ATS’23), October 2023, Beijing, China, 2023.
LibreCat: /record/46738

Workload-Aware Periodic Interconnect BIST
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &;Test (2023) 1–1.
LibreCat: /record/46264
DOI: 10.1109/mdat.2023.3298849

Robust Pattern Generation for Small Delay Faults under Process Variations
H. Jafarzadeh, F. Klemme, J.D. Reimer, Z.P. Najafi Haghi, H.  Amrouch, S. Hellebrand, H.-J.  Wunderlich, in: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, Anaheim, CA, USA, 2023.
LibreCat: /record/45830

Stress-Aware Periodic Test of Interconnects
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing (2022).
LibreCat: /record/29351
DOI: 10.1007/s10836-021-05979-5

EM-Aware Interconnect BIST
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, EM-Aware Interconnect BIST, European Workshop on Silicon Lifecycle Management, March 18, 2022, Online, 2022.
LibreCat: /record/29890

Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study
A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.
LibreCat: /record/19422

Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
S. Sadeghi-Kohan, S. Hellebrand, Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects, 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, Ludwigsburg, 2020.
LibreCat: /record/15419

Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS), IEEE, Virtual Conference - Originally San Diego, CA, USA, 2020.
LibreCat: /record/29200
DOI: 10.1109/vts48691.2020.9107591

Logic Fault Diagnosis of Hidden Delay Defects
S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual Conference - Originally Washington, DC, USA, 2020.
LibreCat: /record/19421

A Hybrid Space Compactor for Varying X-Rates
M.U. Maaz, A. Sprenger, S. Hellebrand, A Hybrid Space Compactor for Varying X-Rates, 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), Prien am Chiemsee, 2019.
LibreCat: /record/8112

Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test
A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers 28 (2019) 1–23.
LibreCat: /record/8667
DOI: 10.1142/s0218126619400012