Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. In: European Test Symposium, The Hague, Netherlands, May 20-24, 2024. IEEE; :6.
LibreCat: /record/52744

Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Vmin Testing under Variations: Defect vs. Fault Coverage. In: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024. IEEE; :6.
LibreCat: /record/52742

Hellebrand S, Sadeghi-Kohan S, Wunderlich H-J. Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. In: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.
LibreCat: /record/52743

Wunderlich H-J, Jafarzadeh H, Hellebrand S. Robust Test of Small Delay Faults under  PVT-Variations. In: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.
LibreCat: /record/52745

Stiballe A, Reimer JD, Sadeghi-Kohan S, Hellebrand S. Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024; 2024.
LibreCat: /record/50284

Ustimova M, Sadeghi-Kohan S, Hellebrand S. Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024; 2024.
LibreCat: /record/51799

Ghazal A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. On Cryptography Effects on Interconnect Reliability. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023; 2023.
LibreCat: /record/35204

Badran A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Approximate Computing: Balancing Performance, Power, Reliability, and Safety. In: 28th IEEE European Test Symposium (ETS’23), May 2023. ; 2023.
LibreCat: /record/41875

Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. In: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). IEEE; 2023. doi:10.1109/dsn-w58399.2023.00056
LibreCat: /record/46739
DOI: 10.1109/dsn-w58399.2023.00056

Sadeghi-Kohan S, Reimer JD, Hellebrand S, Wunderlich H-J. Optimizing the Streaming of Sensor Data with Approximate Communication. In: IEEE Asian Test Symposium (ATS’23), October 2023. ; 2023.
LibreCat: /record/46738

Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect BIST. IEEE Design &;Test. Published online 2023:1-1. doi:10.1109/mdat.2023.3298849
LibreCat: /record/46264
DOI: 10.1109/mdat.2023.3298849

Jafarzadeh H, Klemme F, Reimer JD, et al. Robust Pattern Generation for Small Delay Faults under Process Variations. In: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE; 2023.
LibreCat: /record/45830

Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing. Published online 2022. doi:10.1007/s10836-021-05979-5
LibreCat: /record/29351
DOI: 10.1007/s10836-021-05979-5

Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. EM-Aware Interconnect BIST. European Workshop on Silicon Lifecycle Management, March 18, 2022; 2022.
LibreCat: /record/29890

Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020. ; 2020.
LibreCat: /record/19422

Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020; 2020.
LibreCat: /record/15419

Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. In: 38th IEEE VLSI Test Symposium (VTS). IEEE; 2020. doi:10.1109/vts48691.2020.9107591
LibreCat: /record/29200
DOI: 10.1109/vts48691.2020.9107591

Holst S, Kampmann M, Sprenger A, et al. Logic Fault Diagnosis of Hidden Delay Defects. In: IEEE International Test Conference (ITC’20), November 2020. ; 2020.
LibreCat: /record/19421

Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19); 2019.
LibreCat: /record/8112

Sprenger A, Hellebrand S. Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers. 2019;28(1):1-23. doi:10.1142/s0218126619400012
LibreCat: /record/8667
DOI: 10.1142/s0218126619400012