Validating Statistical Delay Test Generation under Timing Variations via SAT-Based ATPG
H. Jafarzadeh, J.D. Reimer, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: To Appear in: 27th IEEE Latin American Test Symposium (LA), March 2026, Florianopolis, Brazil, 2026.

SAT-Based Validation of Statistical Delay Test Generation under Timing Variations
H. Jafarzadeh, J.D. Reimer, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, SAT-Based Validation of Statistical Delay Test Generation under Timing Variations, Workshop: Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2026), Feb. 2026, 2026.

ThorSim: Throughput-Oriented Timing Simulation of FinFET Digital Circuits
J.D. Reimer, S. Holst, S. Sadeghi-Kohan, H.-J. Wunderlich, S. Hellebrand, in: IEEE International Symposium of Electronics Design Automation (ISEDA’25), May 2025, Hong Kong, China, 2025.

Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression
A. Stiballe, J.D. Reimer, S. Sadeghi-Kohan, S. Hellebrand, Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression, 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, Darmstadt, Germany, 2024.

Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing
H. Jafarzadeh, F. Klemme, J.D. Reimer, H.  Amrouch, S. Hellebrand, H.-J. Wunderlich, in: In: IEEE International Test Conference (ITC’24), San Diego, CA, USA, November 2024, IEEE, San Diego, CA, 2024.

Optimizing the Streaming of Sensor Data with Approximate Communication
S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, in: IEEE Asian Test Symposium (ATS’23), October 2023, Beijing, China, 2023.

Robust Pattern Generation for Small Delay Faults under Process Variations
H. Jafarzadeh, F. Klemme, J.D. Reimer, Z.P. Najafi Haghi, H.  Amrouch, S. Hellebrand, H.-J.  Wunderlich, in: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, Anaheim, CA, USA, 2023.

On Cryptography Effects on Interconnect Reliability
A. Ghazal, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, On Cryptography Effects on Interconnect Reliability, 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, Erfurt, Germany, 2023.

Approximate Computing: Balancing Performance, Power, Reliability, and Safety
A. Badran, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: 28th IEEE European Test Symposium (ETS’23), May 2023, Venice, Italy, 2023.

Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study
A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.

Logic Fault Diagnosis of Hidden Delay Defects
S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual Conference - Originally Washington, DC, USA, 2020.