Awais M, Ghasemzadeh Mohammadi H, Platzner M. An MCTS-based Framework for Synthesis of Approximate Circuits. In: 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). ; 2018:219-224. doi:10.1109/VLSI-SoC.2018.8645026

Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016;PP(99):1-1. doi:10.1109/TCAD.2016.2547908

Ghasemzadeh Mohammadi H, Gaillardon P-E, Zhang J, Micheli GD, Sanchez E, Reorda MS. A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. ACM Journal on Emerging Technologies in Computing Systems. 2016:1-13. doi:10.1145/2988234

Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. IEEE Transactions on Nanotechnology. 2015;14(6):1117-1126. doi:10.1109/TNANO.2015.2482359

Ghasemzadeh Mohammadi H, Gaillardon P-E, Zhang J, De Micheli G, Sanchez E, Reorda MS. On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors. In: 2015 IEEE Computer Society Annual Symposium on VLSI. IEEE; 2015:491-496. doi:10.1109/ISVLSI.2015.13

Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Fault modeling in controllable polarity silicon nanowire circuits. In: Proceedings of the 2015 Design, Automation &; Test in Europe Conference \'26; Exhibition. EDA Consortium; 2015:453-458. doi:10.7873/DATE.2015.0428

Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. In: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE; 2014:163-168. doi:10.1109/NANOARCH.2014.6880479

Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. A fast TCAD-based methodology for Variation analysis of emerging nano-devices. In: 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS). IEEE; 2013:83-88. doi:10.1109/DFT.2013.6653587

Gaillardon P-E, Ghasemzadeh Mohammadi H, De Micheli G. Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. In: 2013 14th Latin American Test Workshop-LATW. IEEE; 2013:1-6. doi:10.1109/LATW.2013.6562673

Khatir M, Ghasemzadeh Mohammadi H, Ejlali A. Sub-threshold charge recovery circuits. In: Computer Design (ICCD), 2010 IEEE International Conference On. IEEE; 2010:138-144. doi:10.1109/ICCD.2010.5647815

Ghasemzadeh Mohammadi H, Miremadi SG, Ejlali A. Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors. In: Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On. IEEE; 2009:252-255. doi:10.1109/PRDC.2009.69

Ghasemzadeh Mohammadi H, Tabkhi H, Miremadi SG, Ejlali A. A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic. In: 2008 International Conference on Microelectronics. IEEE; 2008:444-447. doi:10.1109/ICM.2008.5393497