Bauer, C., Kenter, T., Lass, M., Mazur, L., Meyer, M., Nitsche, H., Riebler, H., Schade, R., Schwarz, M., Winnwa, N., Wiens, A., Wu, X., Plessl, C., &; Simon, J. (2024). Noctua 2 Supercomputer. Journal of Large-Scale Research Facilities, 9.https://doi.org/10.17815/jlsrf-8-187  

Van Hirtum, L., De Causmaecker, P., Goemaere, J., Kenter, T., Riebler, H., Lass, M., &; Plessl, C. (2023). A computation of D(9) using FPGA Supercomputing. In arXiv:2304.03039.

Hansmeier, T., Kenter, T., Meyer, M., Riebler, H., Platzner, M., &; Plessl, C. (2023). Compute Centers I: Heterogeneous Execution Environments. In C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, &; H. Wehrheim (Eds.), On-The-Fly Computing -- Individualized IT-services in dynamic markets (Vol. 412, pp. 165–182). Heinz Nixdorf Institut, Universität Paderborn.https://doi.org/10.5281/zenodo.8068642 

Riebler, H., Vaz, G. F., Kenter, T., &; Plessl, C. (2019). Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL. ACM Trans. Archit. Code Optim. (TACO), 16(2), 14:1–14:26.https://doi.org/10.1145/3319423 

Riebler, H. (2019). Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs.https://doi.org/10.17619/UNIPB/1-830 

Riebler, H., Vaz, G. F., Kenter, T., &; Plessl, C. (2018). Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP).https://doi.org/10.1145/3178487.3178534 

Riebler, H., Lass, M., Mittendorf, R., Löcke, T., &; Plessl, C. (2017). Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 10(3), 24:1-24:23.https://doi.org/10.1145/3053687 

Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., &; Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proc. HiPEAC Workshop on Reonfigurable Computing (WRC).

Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., &; Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5.https://doi.org/10.1109/RTSI.2016.7740545 

Vaz, G. F., Riebler, H., Kenter, T., &; Plessl, C. (2016). Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering, 55, 91–111.https://doi.org/10.1016/j.compeleceng.2016.04.021 

Kenter, T., Vaz, G. F., Riebler, H., &; Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). Workshop on Reconfigurable Computing (WRC).

Damschen, M., Riebler, H., Vaz, G. F., &; Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083.https://doi.org/10.7873/DATE.2015.1124 

Riebler, H., Kenter, T., Plessl, C., &; Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229.https://doi.org/10.1109/FCCM.2014.67 

C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., &; Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149.https://doi.org/10.1109/ISPA.2014.27 

Vaz, G. F., Riebler, H., Kenter, T., &; Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8.https://doi.org/10.1109/ReConFig.2014.7032509 

Riebler, H. (2013). Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn.

Riebler, H. (2013). Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Paderborn University.

Riebler, H., Kenter, T., Sorge, C., &; Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389.https://doi.org/10.1109/FPT.2013.6718394