Bauer, Carsten, et al. “Noctua 2 Supercomputer.”10.17815/jlsrf-8-187 __Journal of Large-Scale Research Facilities, vol. 9, 2024, doi:10.17815/jlsrf-8-187 .

Van Hirtum, Lennart, et al. “A Computation of D(9) Using FPGA Supercomputing.” ArXiv:2304.03039, 2023.

Hansmeier, Tim, et al. “Compute Centers I: Heterogeneous Execution Environments.”10.5281/zenodo.8068642__On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, edited by Claus-Jochen Haake et al., vol. 412, Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 165–82, doi:10.5281/zenodo.8068642.

Riebler, Heinrich, et al. “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL.”10.1145/3319423__ACM Trans. Archit. Code Optim. (TACO), vol. 16, no. 2, ACM, 2019, pp. 14:1–14:26, doi:10.1145/3319423.

Riebler, Heinrich. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs. 2019, doi:10.17619/UNIPB/1-830.

Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.”10.1145/3178487.3178534__Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018, doi:10.1145/3178487.3178534.

Riebler, Heinrich, et al. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.”10.1145/3053687__ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, Association for Computing Machinery (ACM), 2017, p. 24:1-24:23, doi:10.1145/3053687.

Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.

Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.”10.1109/RTSI.2016.7740545__Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5, doi:10.1109/RTSI.2016.7740545.

Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.”10.1016/j.compeleceng.2016.04.021__Computers and Electrical Engineering, vol. 55, Elsevier, 2016, pp. 91–111, doi:10.1016/j.compeleceng.2016.04.021.

Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable Computing (WRC), 2016.

Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.”10.7873/DATE.2015.1124__Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124.

Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.”10.1109/FCCM.2014.67__Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.

C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.”10.1109/ISPA.2014.27__Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.

Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.”10.1109/ReConFig.2014.7032509__Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.

Riebler, Heinrich. Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn, 2013.

Riebler, Heinrich. Identifikation Und Wiederherstellung von Kryptographischen Schlüsseln Mit FPGAs. Paderborn University, 2013.

Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.”10.1109/FPT.2013.6718394__Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.