Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., &; Wunderlich, H.-J. (n.d.). Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. European Test Symposium, The Hague, Netherlands, May 20-24, 2024, 6.
LibreCat: /record/52744

Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., &; Wunderlich, H.-J. (n.d.). Vmin Testing under Variations: Defect vs. Fault Coverage. IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, 6.
LibreCat: /record/52742

Hellebrand, S., Sadeghi-Kohan, S., &; Wunderlich, H.-J. (n.d.). Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.
LibreCat: /record/52743

Wunderlich, H.-J., Jafarzadeh, H., &; Hellebrand, S. (n.d.). Robust Test of Small Delay Faults under  PVT-Variations. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.
LibreCat: /record/52745

Sadeghi-Kohan, S., Hellebrand, S., &; Wunderlich, H.-J. (2023). Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W).https://doi.org/10.1109/dsn-w58399.2023.00056 
LibreCat: /record/46739
DOI: 10.1109/dsn-w58399.2023.00056

Sadeghi-Kohan, S., Reimer, J. D., Hellebrand, S., &; Wunderlich, H.-J. (2023). Optimizing the Streaming of Sensor Data with Approximate Communication. IEEE Asian Test Symposium (ATS’23), October 2023. IEEE Asian Test Symposium (ATS’23).
LibreCat: /record/46738

Jafarzadeh, H., Klemme, F., Reimer, J. D., Najafi Haghi, Z. P.,  Amrouch, H., Hellebrand, S., &;  Wunderlich, H.-J. (2023). Robust Pattern Generation for Small Delay Faults under Process Variations. IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE International Test Conference (ITC’23), Anaheim, USA.
LibreCat: /record/45830

Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., &; Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020.
LibreCat: /record/19422

Sadeghi-Kohan, S., &; Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 38th IEEE VLSI Test Symposium (VTS).https://doi.org/10.1109/vts48691.2020.9107591 
LibreCat: /record/29200
DOI: 10.1109/vts48691.2020.9107591

Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich, H.-J., &; Weng, X. (2020). Logic Fault Diagnosis of Hidden Delay Defects. IEEE International Test Conference (ITC’20), November 2020.
LibreCat: /record/19421

Maaz, M. U., Sprenger, A., &; Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. 50th IEEE International Test Conference (ITC), 1–8.
LibreCat: /record/12918

Rezaeizadeh Rookerd, R., Sadeghi-Kohan, S., &; Navabi, Z. (2018). Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. Proceedings of the 2018 on Great Lakes Symposium on VLSI.https://doi.org/10.1145/3194554.3194599 
LibreCat: /record/29460
DOI: 10.1145/3194554.3194599

Sprenger, A., &; Hellebrand, S. (2018). Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &; Systems (DDECS).https://doi.org/10.1109/ddecs.2018.00020 
LibreCat: /record/4575
DOI: 10.1109/ddecs.2018.00020

Liu, C., Schneider, E., Kampmann, M., Hellebrand, S., &; Wunderlich, H.-J. (2018). Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. 27th IEEE Asian Test Symposium (ATS’18).https://doi.org/10.1109/ats.2018.00028 
LibreCat: /record/10575
DOI: 10.1109/ats.2018.00028

Sadeghi-Kohan, S., Vafaei, A., &; Navabi, Z. (2018). Near-Optimal Node Selection Procedure for Aging Monitor Placement. 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).https://doi.org/10.1109/iolts.2018.8474120 
LibreCat: /record/29459
DOI: 10.1109/iolts.2018.8474120

Deshmukh, J., Kunz, W., Wunderlich, H.-J., &; Hellebrand, S. (2017). Special Session on Early Life Failures. In 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE.https://doi.org/10.1109/vts.2017.7928933 
LibreCat: /record/12973
DOI: 10.1109/vts.2017.7928933

Kampmann, M., &; Hellebrand, S. (2017). Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. 20th IEEE International Symposium on Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’17).https://doi.org/10.1109/ddecs.2017.7934564 
LibreCat: /record/10576
DOI: 10.1109/ddecs.2017.7934564

Jenihhin, M., Kamkin, A., Navabi, Z., &; Sadeghi-Kohan, S. (2017). Universal mitigation of NBTI-induced aging by design randomization. 2016 IEEE East-West Design &; Test Symposium (EWDTS).https://doi.org/10.1109/ewdts.2016.7807635 
LibreCat: /record/29463
DOI: 10.1109/ewdts.2016.7807635

Kampmann, M., &; Hellebrand, S. (2016). X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. In 25th IEEE Asian Test Symposium (ATS’16) (pp. 1–6). Hiroshima, Japan: IEEE.https://doi.org/10.1109/ats.2016.20 
LibreCat: /record/12975
DOI: 10.1109/ats.2016.20

Kampmann, M., A. Kochte, M., Schneider, E., Indlekofer, T., Hellebrand, S., &; Wunderlich, H.-J. (2015). Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In 24th IEEE Asian Test Symposium (ATS’15) (pp. 109–114). Mumbai, India: IEEE.https://doi.org/10.1109/ats.2015.26 
LibreCat: /record/12976
DOI: 10.1109/ats.2015.26

Sadeghi-Kohan, S., Kamran, A., Forooghifar, F., &; Navabi, Z. (2015). Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. 2015 10th International Conference on Design &; Technology of Integrated Systems in Nanoscale Era (DTIS).https://doi.org/10.1109/dtis.2015.7127373 
LibreCat: /record/29465
DOI: 10.1109/dtis.2015.7127373

Sadeghi-Kohan, S., Kamal, M., McNeil, J., Prinetto, P., &; Navabi, Z. (2015). Online self adjusting progressive age monitoring of timing variations. 2015 10th International Conference on Design &; Technology of Integrated Systems in Nanoscale Era (DTIS).https://doi.org/10.1109/dtis.2015.7127368 
LibreCat: /record/29466
DOI: 10.1109/dtis.2015.7127368

Hellebrand, S., Indlekofer, T., Kampmann, M., A. Kochte, M., Liu, C., &; Wunderlich, H.-J. (2014). FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In IEEE International Test Conference (ITC’14). Seattle, Washington, USA: IEEE.https://doi.org/10.1109/test.2014.7035360 
LibreCat: /record/12977
DOI: 10.1109/test.2014.7035360

Mohammadi, M., Sadeghi-Kohan, S., Masoumi, N., &; Navabi, Z. (2014). An off-line MDSI interconnect BIST incorporated in BS 1149.1. 2014 19th IEEE European Test Symposium (ETS).https://doi.org/10.1109/ets.2014.6847847 
LibreCat: /record/46268
DOI: 10.1109/ets.2014.6847847

Sadeghi-Kohan, S., Behnam, P., Alizadeh, B., Fujita, M., &; Navabi, Z. (2014). Improving polynomial datapath debugging with HEDs. 2014 19th IEEE European Test Symposium (ETS).https://doi.org/10.1109/ets.2014.6847797 
LibreCat: /record/46267
DOI: 10.1109/ets.2014.6847797

Hellebrand, S. (2013). Analyzing and Quantifying Fault Tolerance Properties. In 14th IEEE Latin American Test Workshop - (LATW’13). Cordoba, Argentina: IEEE.https://doi.org/10.1109/latw.2013.6562662 
LibreCat: /record/12979
DOI: 10.1109/latw.2013.6562662

Sadeghi-Kohan, S., Namaki-Shoushtari, M., Javaheri, F., &; Navabi, Z. (2013). BS 1149.1 extensions for an online interconnect fault detection and recovery. 2012 IEEE International Test Conference.https://doi.org/10.1109/test.2012.6401583 
LibreCat: /record/46271
DOI: 10.1109/test.2012.6401583

Sadeghi-Kohan, S., Keshavarz, S., Zokaee, F., Farahmandi, F., &; Navabi, Z. (2013). A new structure for interconnect offline testing. East-West Design &;amp; Test Symposium (EWDTS 2013).https://doi.org/10.1109/ewdts.2013.6673207 
LibreCat: /record/46270
DOI: 10.1109/ewdts.2013.6673207

Cook, A., Hellebrand, S., E. Imhof, M., Mumtaz, A., &; Wunderlich, H.-J. (2012). Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. In 13th IEEE Latin American Test Workshop (LATW’12) (pp. 1–4). Quito, Ecuador: IEEE.https://doi.org/10.1109/latw.2012.6261229 
LibreCat: /record/12980
DOI: 10.1109/latw.2012.6261229

Cook, A., Hellebrand, S., &; Wunderlich, H.-J. (2012). Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. In 17th IEEE European Test Symposium (ETS’12) (pp. 1–6). Annecy, France: IEEE.https://doi.org/10.1109/ets.2012.6233025 
LibreCat: /record/12981
DOI: 10.1109/ets.2012.6233025

Cook, A., Hellebrand, S., Indlekofer, T., &; Wunderlich, H.-J. (2011). Diagnostic Test of Robust Circuits. In 20th IEEE Asian Test Symposium (ATS’11) (pp. 285–290). New Delhi, India: IEEE.https://doi.org/10.1109/ats.2011.55 
LibreCat: /record/12982
DOI: 10.1109/ats.2011.55

Polian, I., Becker, B., Hellebrand, S., Wunderlich, H.-J., &; Maxwell, P. (2011). Towards Variation-Aware Test Methods. In 16th IEEE European Test Symposium Trondheim (ETS’11). Trondheim, Norway: IEEE.https://doi.org/10.1109/ets.2011.51 
LibreCat: /record/12984
DOI: 10.1109/ets.2011.51

Cook, A., Hellebrand, S., Indlekofer, T., &; Wunderlich, H.-J. (2011). Robuster Selbsttest mit Diagnose. In 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit und Entwurf” (pp. 48–53). Hamburg, Germany.
LibreCat: /record/13053

Kamran, A., Nemati, N., Sadeghi-Kohan, S., &; Navabi, Z. (2011). Virtual tester development using HDL/PLI. 2010 East-West Design &;amp; Test Symposium (EWDTS).https://doi.org/10.1109/ewdts.2010.5742156 
LibreCat: /record/46272
DOI: 10.1109/ewdts.2010.5742156

Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10). Chicago, IL, USA: IEEE.https://doi.org/10.1109/dsnw.2010.5542612 
LibreCat: /record/12987
DOI: 10.1109/dsnw.2010.5542612

Hunger, M., &; Hellebrand, S. (2010). Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf” (pp. 81–88). Wildbad Kreuth, Germany.
LibreCat: /record/13051

Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2010). Variation-Aware Fault Modeling. 19th IEEE Asian Test Symposium (ATS’10), 87–93.https://doi.org/10.1109/ats.2010.24 
LibreCat: /record/12983
DOI: 10.1109/ats.2010.24

Indlekofer, T., Schnittger, M., &; Hellebrand, S. (2010). Efficient Test Response Compaction for Robust BIST Using Parity Sequences. 28th IEEE International Conference on Computer Design (ICCD’10), 480–485.https://doi.org/10.1109/iccd.2010.5647648 
LibreCat: /record/12985
DOI: 10.1109/iccd.2010.5647648

Hunger, M., &; Hellebrand, S. (2010). The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 101–108.https://doi.org/10.1109/dft.2010.19 
LibreCat: /record/12986
DOI: 10.1109/dft.2010.19

Froese, V., Ibers, R., &; Hellebrand, S. (2010). Reusing NoC-Infrastructure for Test Data Compression. 28th IEEE VLSI Test Symposium (VTS’10), 227–231.https://doi.org/10.1109/vts.2010.5469570 
LibreCat: /record/12988
DOI: 10.1109/vts.2010.5469570

Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper).
LibreCat: /record/13049

Indlekofer, T., Schnittger, M., &; Hellebrand, S. (2010). Robuster Selbsttest mit extremer Kompaktierung. 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 17–24.
LibreCat: /record/13050

Hunger, M., Hellebrand, S., Czutro, A., Polian, I., &; Becker, B. (2009). ATPG-Based Grading of Strong Fault-Secureness. 15th IEEE International On-Line Testing Symposium (IOLTS’09.https://doi.org/10.1109/iolts.2009.5196027 
LibreCat: /record/12991
DOI: 10.1109/iolts.2009.5196027

Hellebrand, S., &; Hunger, M. (2009). Are Robust Circuits Really Robust? 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 77.https://doi.org/10.1109/dft.2009.28 
LibreCat: /record/12990
DOI: 10.1109/dft.2009.28

Hunger, M., Hellebrand, S., Czutro, A., Polian, I., &; Becker, B. (2009). Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”
LibreCat: /record/13030

Oehler, P., Bosio, A., di Natale, G., &; Hellebrand, S. (2008). A Modular Memory BIST for Optimized Memory Repair. 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster).https://doi.org/10.1109/iolts.2008.30 
LibreCat: /record/12992
DOI: 10.1109/iolts.2008.30

Amgalan, U., Hachmann, C., Hellebrand, S., &; Wunderlich, H.-J. (2008). Signature Rollback - A Technique for Testing Robust Circuits. 26th IEEE VLSI Test Symposium (VTS’08), 125–130.https://doi.org/10.1109/vts.2008.34 
LibreCat: /record/12994
DOI: 10.1109/vts.2008.34

Hunger, M., &; Hellebrand, S. (2008). Verification and Analysis of Self-Checking Properties through ATPG. 14th IEEE International On-Line Testing Symposium (IOLTS’08).https://doi.org/10.1109/iolts.2008.32 
LibreCat: /record/12993
DOI: 10.1109/iolts.2008.32

Hunger, M., &; Hellebrand, S. (2008). Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”
LibreCat: /record/13031

Oehler, P., Bosio, A., Di Natale, G., &; Hellebrand, S. (2008). Modularer Selbsttest und optimierte Reparaturanalyse. 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”
LibreCat: /record/13032

Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., &; Straube, B. (2007). A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), 50–58.https://doi.org/10.1109/dft.2007.43 
LibreCat: /record/12995
DOI: 10.1109/dft.2007.43

Oehler, P., Hellebrand, S., &; Wunderlich, H.-J. (2007). Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 185–190.https://doi.org/10.1109/ddecs.2007.4295278 
LibreCat: /record/12996
DOI: 10.1109/ddecs.2007.4295278

Oehler, P., Hellebrand, S., &; Wunderlich, H.-J. (2007). An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. 12th IEEE European Test Symposium (ETS’07), 91–96.https://doi.org/10.1109/ets.2007.10 
LibreCat: /record/12997
DOI: 10.1109/ets.2007.10

Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., &; Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper).
LibreCat: /record/13037

Ali, M., Welzl, M., Hessler, S., &; Hellebrand, S. (2007). A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip. 4th International Conference on Information Technology: New Generations (ITNG’07), 1027–1032.
LibreCat: /record/13040

Becker, B., Polian, I., Hellebrand, S., Straube, B., &; Wunderlich, H.-J. (2007). Test und Zuverlässigkeit nanoelektronischer Systeme. 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”
LibreCat: /record/13041

Ali, M., Welzl, M., Zwicknagl, M., &; Hellebrand, S. (2005). Considerations for Fault-Tolerant Networks on Chips. IEEE International Conference on Microelectronics (ICM’05).https://doi.org/10.1109/icm.2005.1590063 
LibreCat: /record/12999
DOI: 10.1109/icm.2005.1590063

Oehler, P., &; Hellebrand, S. (2005). Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. 10th IEEE European Test Symposium (ETS’05), 148–153.https://doi.org/10.1109/ets.2005.28 
LibreCat: /record/13000
DOI: 10.1109/ets.2005.28

Ali, M., Welzl, M., &; Hellebrand, S. (2005). A Dynamic Routing Mechanism for Network on Chip. 23rd IEEE NORCHIP Conference, 70–73.https://doi.org/10.1109/norchp.2005.1596991 
LibreCat: /record/12998
DOI: 10.1109/norchp.2005.1596991

Liu Jing, M., Ruehrup, S., Schindelhauer, C., Volbert, K., Dierkes, M., Bellgardt, A.,  Hilleringmann, U. (2004). Sensor Networks with More Features Using Less Hardware. In GOR/NGB Conference Tilburg 2004. Tilburg, Netherlands.
LibreCat: /record/13071

Wuertenberger, A., S. Tautermann, C., &; Hellebrand, S. (2004). Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. IEEE International Test Conference (ITC’04), 926–935.https://doi.org/10.1109/test.2004.1387357 
LibreCat: /record/13001
DOI: 10.1109/test.2004.1387357

Wuertenberger, A., S. Tautermann, C., &; Hellebrand, S. (2003). A Hybrid Coding Strategy for Optimized Test Data Compression. IEEE International Test Conference (ITC’03), 451–459.https://doi.org/10.1109/test.2003.1270870 
LibreCat: /record/13002
DOI: 10.1109/test.2003.1270870

Liang, H.-G., Hellebrand, S., &; Wunderlich, H.-J. (2001). Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE International Test Conference (ITC’01), 894–902.https://doi.org/10.1109/test.2001.966712 
LibreCat: /record/13004
DOI: 10.1109/test.2001.966712

Hellebrand, S., Liang, H.-G., &; Wunderlich, H.-J. (2000). A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE International Test Conference (ITC’00), 778–784.https://doi.org/10.1109/test.2000.894274 
LibreCat: /record/13005
DOI: 10.1109/test.2000.894274

Hellebrand, S., Wunderlich, H.-J., A. Ivaniuk, A., V. Klimets, Y., &; N. Yarmolik, V. (1999). Error Detecting Refreshment for Embedded DRAMs. 17th IEEE VLSI Test Symposium (VTS’99), 384–390.https://doi.org/10.1109/vtest.1999.766693 
LibreCat: /record/13006
DOI: 10.1109/vtest.1999.766693

N. Yarmolik, V., V. Bykov, I., Hellebrand, S., &; Wunderlich, H.-J. (1999). Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. Third European Dependable Computing Conference (EDCC-3).
LibreCat: /record/13066

Hellebrand, S., Wunderlich, H.-J., &; N. Yarmolik, V. (1999). Symmetric Transparent BIST for RAMs. Design Automation and Test in Europe (DATE’99), 702–707.
LibreCat: /record/13067

Hertwig, A., Hellebrand, S., &; Wunderlich, H.-J. (1998). Fast Self-Recovering Controllers. 16th IEEE VLSI Test Symposium (VTS’98), 296–302.https://doi.org/10.1109/vtest.1998.670883 
LibreCat: /record/13007
DOI: 10.1109/vtest.1998.670883

Hellebrand, S., Wunderlich, H.-J., &; N. Yarmolik, V. (1998). Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. Design Automation and Test in Europe (DATE’98), 173–179.https://doi.org/10.1109/date.1998.655853 
LibreCat: /record/13008
DOI: 10.1109/date.1998.655853

N. Yarmolik, V., V. Klimets, Y., Hellebrand, S., &; Wunderlich, H.-J. (1998). New Transparent RAM BIST Based on Self-Adjusting Output Data Compression. Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’98), 27–33.
LibreCat: /record/13063

Tsai, K.-H., Hellebrand, S., Marek-Sadowska, M., &; Rajski, J. (1997). STARBIST: Scan Autocorrelated Random Pattern Generation. 34th ACM/IEEE Design Automation Conference (DAC’97).https://doi.org/10.1109/dac.1997.597194 
LibreCat: /record/13009
DOI: 10.1109/dac.1997.597194

Hellebrand, S., Wunderlich, H.-J., &; Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. IEEE International Test Conference (ITC’96), 195–204.https://doi.org/10.1109/test.1996.556962 
LibreCat: /record/13010
DOI: 10.1109/test.1996.556962

Hellebrand, S., Reeb, B., Tarnick, S., &; Wunderlich, H.-J. (1995). Pattern Generation for a Deterministic BIST Scheme. ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), 88–94.https://doi.org/10.1109/iccad.1995.479997 
LibreCat: /record/13012
DOI: 10.1109/iccad.1995.479997

Hellebrand, S., &; Wunderlich, H.-J. (1994). An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), 110–116.https://doi.org/10.1109/iccad.1994.629752 
LibreCat: /record/13014
DOI: 10.1109/iccad.1994.629752

Hellebrand, S., &; Wunderlich, H.-J. (1994). Synthese schneller selbsttestbarer Steuerwerke. Tagungsband Der GI/GME/ITG-Fachtagung \'26; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, 3–11.
LibreCat: /record/13059

Hellebrand, S., &; Wunderlich, H.-J. (1994). Synthesis of Self-Testable Controllers. European Design and Test Conference (EDAC/ETC/EUROASIC), 580–585.https://doi.org/10.1109/edtc.1994.326815 
LibreCat: /record/13013
DOI: 10.1109/edtc.1994.326815

Venkataraman, S., Rajski, J., Hellebrand, S., &; Tarnick, S. (1993). An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers. ACM/IEEE International Conference on Computer Aided Design (ICCAD’93).https://doi.org/10.1109/iccad.1993.580117 
LibreCat: /record/13015
DOI: 10.1109/iccad.1993.580117

Hellebrand, S., Tarnick, S., Rajski, J., &; Courtois, B. (1992). Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE International Test Conference (ITC’92), 120–129.https://doi.org/10.1109/test.1992.527812 
LibreCat: /record/13016
DOI: 10.1109/test.1992.527812

Hellebrand, S., &; Wunderlich, H.-J. (1990). Tools and Devices Supporting the Pseudo-Exhaustive Test. European Design Automation Conference (EDAC’90), 13–17.https://doi.org/10.1109/edac.1990.136612 
LibreCat: /record/13018
DOI: 10.1109/edac.1990.136612

Hellebrand, S., Wunderlich, H.-J., &; F. Haberl, O. (1990). Generating Pseudo-Exhaustive Vectors for External Testing. IEEE International Test Conference (ITC’90), 670–679.https://doi.org/10.1109/test.1990.114082 
LibreCat: /record/13019
DOI: 10.1109/test.1990.114082

Wunderlich, H.-J., &; Hellebrand, S. (1989). The Pseudo-Exhaustive Test of Sequential Circuits. IEEE International Test Conference (ITC’89), 19–27.https://doi.org/10.1109/test.1989.82273 
LibreCat: /record/13020
DOI: 10.1109/test.1989.82273

Wunderlich, H.-J., &; Hellebrand, S. (1988). Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits. 18th International Symposium on Fault-Tolerant Computing, FTCS-18, 36–45.https://doi.org/10.1109/ftcs.1988.5294 
LibreCat: /record/13021
DOI: 10.1109/ftcs.1988.5294

Schmid, D., Wunderlich, H.-J., Feldbusch, F., Hellebrand, S., Holzinger, J., &; Kunzmann, A. (1988). Integrated Tools for Automatic Design for Testability. Tool Integration and Design Environments, F.J. Rammig (Editor), 233–258.
LibreCat: /record/13058

Hellebrand, S., &; Wunderlich, H.-J. (1988). Automatisierung des Entwurfs vollständig testbarer Schaltungen. GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188, 145–159.
LibreCat: /record/13062