H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, and H.-J. Wunderlich, “Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations,” in European Test Symposium, The Hague, Netherlands, May 20-24, 2024, The Hague, NL, p. 6.
LibreCat: /record/52744

H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, and H.-J. Wunderlich, “Vmin Testing under Variations: Defect vs. Fault Coverage,” in IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, Maceió, p. 6.
LibreCat: /record/52742

S. Hellebrand, S. Sadeghi-Kohan, and H.-J. Wunderlich, “Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle,” in International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, Xi’an, China, p. 1.
LibreCat: /record/52743

H.-J. Wunderlich, H. Jafarzadeh, and S. Hellebrand, “Robust Test of Small Delay Faults under  PVT-Variations,” in International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, Xi’an, China, p. 1.
LibreCat: /record/52745

S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication,”10.1109/dsn-w58399.2023.00056__2023, doi:10.1109/dsn-w58399.2023.00056 .
LibreCat: /record/46739
DOI: 10.1109/dsn-w58399.2023.00056

S. Sadeghi-Kohan, J. D. Reimer, S. Hellebrand, and H.-J. Wunderlich, “Optimizing the Streaming of Sensor Data with Approximate Communication,” presented at the IEEE Asian Test Symposium (ATS’23), 2023.
LibreCat: /record/46738

H. Jafarzadeh et al., “Robust Pattern Generation for Small Delay Faults under Process Variations,” presented at the IEEE International Test Conference (ITC’23), Anaheim, USA, 2023.
LibreCat: /record/45830

A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study,” 2020.
LibreCat: /record/19422

S. Sadeghi-Kohan and S. Hellebrand, “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects,”10.1109/vts48691.2020.9107591__2020, doi:10.1109/vts48691.2020.9107591 .
LibreCat: /record/29200
DOI: 10.1109/vts48691.2020.9107591

S. Holst et al., “Logic Fault Diagnosis of Hidden Delay Defects,” 2020.
LibreCat: /record/19421

M. U. Maaz, A. Sprenger, and S. Hellebrand, “A Hybrid Space Compactor for Adaptive X-Handling,” in 50th IEEE International Test Conference (ITC), Washington, DC, USA, 2019, pp. 1–8.
LibreCat: /record/12918

R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, and Z. Navabi, “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture,”10.1145/3194554.3194599__2018, doi:10.1145/3194554.3194599 .
LibreCat: /record/29460
DOI: 10.1145/3194554.3194599

A. Sprenger and S. Hellebrand, “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test,”10.1109/ddecs.2018.00020__2018, doi:10.1109/ddecs.2018.00020 .
LibreCat: /record/4575
DOI: 10.1109/ddecs.2018.00020

C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, and H.-J. Wunderlich, “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention,”10.1109/ats.2018.00028__2018, doi:10.1109/ats.2018.00028 .
LibreCat: /record/10575
DOI: 10.1109/ats.2018.00028

S. Sadeghi-Kohan, A. Vafaei, and Z. Navabi, “Near-Optimal Node Selection Procedure for Aging Monitor Placement,”10.1109/iolts.2018.8474120__2018, doi:10.1109/iolts.2018.8474120 .
LibreCat: /record/29459
DOI: 10.1109/iolts.2018.8474120

J. Deshmukh, W. Kunz, H.-J. Wunderlich, and S. Hellebrand, “Special Session on Early Life Failures,” in 35th IEEE VLSI Test Symposium (VTS’17), 2017.
LibreCat: /record/12973
DOI: 10.1109/vts.2017.7928933

M. Kampmann and S. Hellebrand, “Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test,”10.1109/ddecs.2017.7934564__2017, doi:10.1109/ddecs.2017.7934564 .
LibreCat: /record/10576
DOI: 10.1109/ddecs.2017.7934564

M. Jenihhin, A. Kamkin, Z. Navabi, and S. Sadeghi-Kohan, “Universal mitigation of NBTI-induced aging by design randomization,”10.1109/ewdts.2016.7807635__2017, doi:10.1109/ewdts.2016.7807635 .
LibreCat: /record/29463
DOI: 10.1109/ewdts.2016.7807635

M. Kampmann and S. Hellebrand, “X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test,” in 25th IEEE Asian Test Symposium (ATS’16), 2016, pp. 1–6.
LibreCat: /record/12975
DOI: 10.1109/ats.2016.20

M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, and H.-J. Wunderlich, “Optimized Selection of Frequencies for Faster-Than-at-Speed Test,” in 24th IEEE Asian Test Symposium (ATS’15), 2015, pp. 109–114.
LibreCat: /record/12976
DOI: 10.1109/ats.2015.26

S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, and Z. Navabi, “Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation,”10.1109/dtis.2015.7127373__2015, doi:10.1109/dtis.2015.7127373 .
LibreCat: /record/29465
DOI: 10.1109/dtis.2015.7127373

S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, and Z. Navabi, “Online self adjusting progressive age monitoring of timing variations,”10.1109/dtis.2015.7127368__2015, doi:10.1109/dtis.2015.7127368 .
LibreCat: /record/29466
DOI: 10.1109/dtis.2015.7127368

S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, and H.-J. Wunderlich, “FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects,” in IEEE International Test Conference (ITC’14), 2014.
LibreCat: /record/12977
DOI: 10.1109/test.2014.7035360

M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, and Z. Navabi, “An off-line MDSI interconnect BIST incorporated in BS 1149.1,”10.1109/ets.2014.6847847__2014, doi:10.1109/ets.2014.6847847 .
LibreCat: /record/46268
DOI: 10.1109/ets.2014.6847847

S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, and Z. Navabi, “Improving polynomial datapath debugging with HEDs,”10.1109/ets.2014.6847797__2014, doi:10.1109/ets.2014.6847797 .
LibreCat: /record/46267
DOI: 10.1109/ets.2014.6847797

S. Hellebrand, “Analyzing and Quantifying Fault Tolerance Properties,” in 14th IEEE Latin American Test Workshop - (LATW’13), 2013.
LibreCat: /record/12979
DOI: 10.1109/latw.2013.6562662

S. Sadeghi-Kohan, M. Namaki-Shoushtari, F. Javaheri, and Z. Navabi, “BS 1149.1 extensions for an online interconnect fault detection and recovery,”10.1109/test.2012.6401583__2013, doi:10.1109/test.2012.6401583 .
LibreCat: /record/46271
DOI: 10.1109/test.2012.6401583

S. Sadeghi-Kohan, S. Keshavarz, F. Zokaee, F. Farahmandi, and Z. Navabi, “A new structure for interconnect offline testing,”10.1109/ewdts.2013.6673207__2013, doi:10.1109/ewdts.2013.6673207 .
LibreCat: /record/46270
DOI: 10.1109/ewdts.2013.6673207

A. Cook, S. Hellebrand, M. E. Imhof, A. Mumtaz, and H.-J. Wunderlich, “Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test,” in 13th IEEE Latin American Test Workshop (LATW’12), 2012, pp. 1–4.
LibreCat: /record/12980
DOI: 10.1109/latw.2012.6261229

A. Cook, S. Hellebrand, and H.-J. Wunderlich, “Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test,” in 17th IEEE European Test Symposium (ETS’12), 2012, pp. 1–6.
LibreCat: /record/12981
DOI: 10.1109/ets.2012.6233025

A. Cook, S. Hellebrand, T. Indlekofer, and H.-J. Wunderlich, “Diagnostic Test of Robust Circuits,” in 20th IEEE Asian Test Symposium (ATS’11), 2011, pp. 285–290.
LibreCat: /record/12982
DOI: 10.1109/ats.2011.55

I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, and P. Maxwell, “Towards Variation-Aware Test Methods,” in 16th IEEE European Test Symposium Trondheim (ETS’11), 2011.
LibreCat: /record/12984
DOI: 10.1109/ets.2011.51

A. Cook, S. Hellebrand, T. Indlekofer, and H.-J. Wunderlich, “Robuster Selbsttest mit Diagnose,” in 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit und Entwurf,” 2011, pp. 48–53.
LibreCat: /record/13053

A. Kamran, N. Nemati, S. Sadeghi-Kohan, and Z. Navabi, “Virtual tester development using HDL/PLI,”10.1109/ewdts.2010.5742156__2011, doi:10.1109/ewdts.2010.5742156 .
LibreCat: /record/46272
DOI: 10.1109/ewdts.2010.5742156

B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” in 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), 2010.
LibreCat: /record/12987
DOI: 10.1109/dsnw.2010.5542612

M. Hunger and S. Hellebrand, “Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 81–88.
LibreCat: /record/13051

F. Hopsch et al., “Variation-Aware Fault Modeling,”10.1109/ats.2010.24__in 19th IEEE Asian Test Symposium (ATS’10), 2010, pp. 87–93, doi:10.1109/ats.2010.24 .
LibreCat: /record/12983
DOI: 10.1109/ats.2010.24

T. Indlekofer, M. Schnittger, and S. Hellebrand, “Efficient Test Response Compaction for Robust BIST Using Parity Sequences,”10.1109/iccd.2010.5647648__in 28th IEEE International Conference on Computer Design (ICCD’10), 2010, pp. 480–485, doi:10.1109/iccd.2010.5647648 .
LibreCat: /record/12985
DOI: 10.1109/iccd.2010.5647648

M. Hunger and S. Hellebrand, “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems,”10.1109/dft.2010.19__in 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 2010, pp. 101–108, doi:10.1109/dft.2010.19 .
LibreCat: /record/12986
DOI: 10.1109/dft.2010.19

V. Froese, R. Ibers, and S. Hellebrand, “Reusing NoC-Infrastructure for Test Data Compression,”10.1109/vts.2010.5469570__in 28th IEEE VLSI Test Symposium (VTS’10), 2010, pp. 227–231, doi:10.1109/vts.2010.5469570 .
LibreCat: /record/12988
DOI: 10.1109/vts.2010.5469570

B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” 2010.
LibreCat: /record/13049

T. Indlekofer, M. Schnittger, and S. Hellebrand, “Robuster Selbsttest mit extremer Kompaktierung,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 17–24.
LibreCat: /record/13050

M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “ATPG-Based Grading of Strong Fault-Secureness,”10.1109/iolts.2009.5196027__2009, doi:10.1109/iolts.2009.5196027 .
LibreCat: /record/12991
DOI: 10.1109/iolts.2009.5196027

S. Hellebrand and M. Hunger, “Are Robust Circuits Really Robust?,”10.1109/dft.2009.28__in 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 2009, p. 77, doi:10.1109/dft.2009.28 .
LibreCat: /record/12990
DOI: 10.1109/dft.2009.28

M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung,” 2009.
LibreCat: /record/13030

P. Oehler, A. Bosio, G. di Natale, and S. Hellebrand, “A Modular Memory BIST for Optimized Memory Repair,”10.1109/iolts.2008.30__2008, doi:10.1109/iolts.2008.30 .
LibreCat: /record/12992
DOI: 10.1109/iolts.2008.30

U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, “Signature Rollback - A Technique for Testing Robust Circuits,”10.1109/vts.2008.34__in 26th IEEE VLSI Test Symposium (VTS’08), 2008, pp. 125–130, doi:10.1109/vts.2008.34 .
LibreCat: /record/12994
DOI: 10.1109/vts.2008.34

M. Hunger and S. Hellebrand, “Verification and Analysis of Self-Checking Properties through ATPG,”10.1109/iolts.2008.32__2008, doi:10.1109/iolts.2008.32 .
LibreCat: /record/12993
DOI: 10.1109/iolts.2008.32

M. Hunger and S. Hellebrand, “Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG,” 2008.
LibreCat: /record/13031

P. Oehler, A. Bosio, G. Di Natale, and S. Hellebrand, “Modularer Selbsttest und optimierte Reparaturanalyse,” 2008.
LibreCat: /record/13032

S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction,”10.1109/dft.2007.43__in 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), 2007, pp. 50–58, doi:10.1109/dft.2007.43 .
LibreCat: /record/12995
DOI: 10.1109/dft.2007.43

P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair,”10.1109/ddecs.2007.4295278__in 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 2007, pp. 185–190, doi:10.1109/ddecs.2007.4295278 .
LibreCat: /record/12996
DOI: 10.1109/ddecs.2007.4295278

P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy,”10.1109/ets.2007.10__in 12th IEEE European Test Symposium (ETS’07), 2007, pp. 91–96, doi:10.1109/ets.2007.10 .
LibreCat: /record/12997
DOI: 10.1109/ets.2007.10

S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance,” 2007.
LibreCat: /record/13037

M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip,” in 4th International Conference on Information Technology: New Generations (ITNG’07), 2007, pp. 1027–1032.
LibreCat: /record/13040

B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, “Test und Zuverlässigkeit nanoelektronischer Systeme,” 2007.
LibreCat: /record/13041

M. Ali, M. Welzl, M. Zwicknagl, and S. Hellebrand, “Considerations for Fault-Tolerant Networks on Chips,”10.1109/icm.2005.1590063__2005, doi:10.1109/icm.2005.1590063 .
LibreCat: /record/12999
DOI: 10.1109/icm.2005.1590063

P. Oehler and S. Hellebrand, “Low Power Embedded DRAMs with High Quality Error Correcting Capabilities,”10.1109/ets.2005.28__in 10th IEEE European Test Symposium (ETS’05), 2005, pp. 148–153, doi:10.1109/ets.2005.28 .
LibreCat: /record/13000
DOI: 10.1109/ets.2005.28

M. Ali, M. Welzl, and S. Hellebrand, “A Dynamic Routing Mechanism for Network on Chip,”10.1109/norchp.2005.1596991__in 23rd IEEE NORCHIP Conference, 2005, pp. 70–73, doi:10.1109/norchp.2005.1596991 .
LibreCat: /record/12998
DOI: 10.1109/norchp.2005.1596991

M. Liu Jing et al., “Sensor Networks with More Features Using Less Hardware,” in GOR/NGB Conference Tilburg 2004, 2004.
LibreCat: /record/13071

A. Wuertenberger, C. S. Tautermann, and S. Hellebrand, “Data Compression for Multiple Scan Chains Using Dictionaries with Corrections,”10.1109/test.2004.1387357__in IEEE International Test Conference (ITC’04), 2004, pp. 926–935, doi:10.1109/test.2004.1387357 .
LibreCat: /record/13001
DOI: 10.1109/test.2004.1387357

A. Wuertenberger, C. S. Tautermann, and S. Hellebrand, “A Hybrid Coding Strategy for Optimized Test Data Compression,”10.1109/test.2003.1270870__in IEEE International Test Conference (ITC’03), 2003, pp. 451–459, doi:10.1109/test.2003.1270870 .
LibreCat: /record/13002
DOI: 10.1109/test.2003.1270870

H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST,”10.1109/test.2001.966712__in IEEE International Test Conference (ITC’01), 2001, pp. 894–902, doi:10.1109/test.2001.966712 .
LibreCat: /record/13004
DOI: 10.1109/test.2001.966712

S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters,”10.1109/test.2000.894274__in IEEE International Test Conference (ITC’00), 2000, pp. 778–784, doi:10.1109/test.2000.894274 .
LibreCat: /record/13005
DOI: 10.1109/test.2000.894274

S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, and V. N. Yarmolik, “Error Detecting Refreshment for Embedded DRAMs,”10.1109/vtest.1999.766693__in 17th IEEE VLSI Test Symposium (VTS’99), 1999, pp. 384–390, doi:10.1109/vtest.1999.766693 .
LibreCat: /record/13006
DOI: 10.1109/vtest.1999.766693

V. N. Yarmolik, I. V. Bykov, S. Hellebrand, and H.-J. Wunderlich, “Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms,” 1999.
LibreCat: /record/13066

S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, “Symmetric Transparent BIST for RAMs,” in Design Automation and Test in Europe (DATE’99), 1999, pp. 702–707.
LibreCat: /record/13067

A. Hertwig, S. Hellebrand, and H.-J. Wunderlich, “Fast Self-Recovering Controllers,”10.1109/vtest.1998.670883__in 16th IEEE VLSI Test Symposium (VTS’98), 1998, pp. 296–302, doi:10.1109/vtest.1998.670883 .
LibreCat: /record/13007
DOI: 10.1109/vtest.1998.670883

S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, “Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs,”10.1109/date.1998.655853__in Design Automation and Test in Europe (DATE’98), 1998, pp. 173–179, doi:10.1109/date.1998.655853 .
LibreCat: /record/13008
DOI: 10.1109/date.1998.655853

V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, and H.-J. Wunderlich, “New Transparent RAM BIST Based on Self-Adjusting Output Data Compression,” in Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’98), 1998, pp. 27–33.
LibreCat: /record/13063

K.-H. Tsai, S. Hellebrand, M. Marek-Sadowska, and J. Rajski, “STARBIST: Scan Autocorrelated Random Pattern Generation,”10.1109/dac.1997.597194__1997, doi:10.1109/dac.1997.597194 .
LibreCat: /record/13009
DOI: 10.1109/dac.1997.597194

S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,”10.1109/test.1996.556962__in IEEE International Test Conference (ITC’96), 1996, pp. 195–204, doi:10.1109/test.1996.556962 .
LibreCat: /record/13010
DOI: 10.1109/test.1996.556962

S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich, “Pattern Generation for a Deterministic BIST Scheme,”10.1109/iccad.1995.479997__in ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), 1995, pp. 88–94, doi:10.1109/iccad.1995.479997 .
LibreCat: /record/13012
DOI: 10.1109/iccad.1995.479997

S. Hellebrand and H.-J. Wunderlich, “An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures,”10.1109/iccad.1994.629752__in ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), 1994, pp. 110–116, doi:10.1109/iccad.1994.629752 .
LibreCat: /record/13014
DOI: 10.1109/iccad.1994.629752

S. Hellebrand and H.-J. Wunderlich, “Synthese schneller selbsttestbarer Steuerwerke,” in Tagungsband der GI/GME/ITG-Fachtagung \'26; Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1994, pp. 3–11.
LibreCat: /record/13059

S. Hellebrand and H.-J. Wunderlich, “Synthesis of Self-Testable Controllers,”10.1109/edtc.1994.326815__in European Design and Test Conference (EDAC/ETC/EUROASIC), 1994, pp. 580–585, doi:10.1109/edtc.1994.326815 .
LibreCat: /record/13013
DOI: 10.1109/edtc.1994.326815

S. Venkataraman, J. Rajski, S. Hellebrand, and S. Tarnick, “An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers,”10.1109/iccad.1993.580117__1993, doi:10.1109/iccad.1993.580117 .
LibreCat: /record/13015
DOI: 10.1109/iccad.1993.580117

S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, “Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,”10.1109/test.1992.527812__in IEEE International Test Conference (ITC’92), 1992, pp. 120–129, doi:10.1109/test.1992.527812 .
LibreCat: /record/13016
DOI: 10.1109/test.1992.527812

S. Hellebrand and H.-J. Wunderlich, “Tools and Devices Supporting the Pseudo-Exhaustive Test,”10.1109/edac.1990.136612__in European Design Automation Conference (EDAC’90), 1990, pp. 13–17, doi:10.1109/edac.1990.136612 .
LibreCat: /record/13018
DOI: 10.1109/edac.1990.136612

S. Hellebrand, H.-J. Wunderlich, and O. F. Haberl, “Generating Pseudo-Exhaustive Vectors for External Testing,”10.1109/test.1990.114082__in IEEE International Test Conference (ITC’90), 1990, pp. 670–679, doi:10.1109/test.1990.114082 .
LibreCat: /record/13019
DOI: 10.1109/test.1990.114082

H.-J. Wunderlich and S. Hellebrand, “The Pseudo-Exhaustive Test of Sequential Circuits,”10.1109/test.1989.82273__in IEEE International Test Conference (ITC’89), 1989, pp. 19–27, doi:10.1109/test.1989.82273 .
LibreCat: /record/13020
DOI: 10.1109/test.1989.82273

H.-J. Wunderlich and S. Hellebrand, “Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits,”10.1109/ftcs.1988.5294__in 18th International Symposium on Fault-Tolerant Computing, FTCS-18, 1988, pp. 36–45, doi:10.1109/ftcs.1988.5294 .
LibreCat: /record/13021
DOI: 10.1109/ftcs.1988.5294

D. Schmid, H.-J. Wunderlich, F. Feldbusch, S. Hellebrand, J. Holzinger, and A. Kunzmann, “Integrated Tools for Automatic Design for Testability,” in Tool Integration and Design Environments, F.J. Rammig (Editor), 1988, pp. 233–258.
LibreCat: /record/13058

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