Lass M, Kenter T, Plessl C, Brehm M. Characterizing Microheterogeneity in Liquid Mixtures via Local Density Fluctuations. Entropy. 2024;26(4). doi:10.3390/e26040322

Büttner M, Alt C, Kenter T, Köstler H, Plessl C, Aizinger V. Enabling Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with SYCL. In: Proceedings of the Platform for Advanced Scientific Computing Conference (PASC). ACM; 2024. doi:10.1145/3659914.3659925

Bauer C, Kenter T, Lass M, et al. Noctua 2 Supercomputer. Journal of large-scale research facilities. 2024;9. doi:10.17815/jlsrf-8-187 

Olgu K, Kenter T, Nunez-Yanez J, Mcintosh-Smith S. Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing Algorithms to Describing Architectures. In: Proceedings of the 12th International Workshop on OpenCL and SYCL. ACM; 2024. doi:10.1145/3648115.3648134

Van Hirtum L, De Causmaecker P, Goemaere J, et al. A computation of D(9) using FPGA Supercomputing. arXiv:230403039. Published online 2023.

Schade R, Kenter T, Elgabarty H, Lass M, Kühne T, Plessl C. Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics. The International Journal of High Performance Computing Applications. Published online 2023. doi:10.1177/10943420231177631

Hansmeier T, Kenter T, Meyer M, Riebler H, Platzner M, Plessl C. Compute Centers I: Heterogeneous Execution Environments. In: Haake C-J, Meyer auf der Heide F, Platzner M, Wachsmuth H, Wehrheim H, eds. On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets. Vol 412. Verlagsschriftenreihe des Heinz Nixdorf Instituts. Heinz Nixdorf Institut, Universität Paderborn; 2023:165-182. doi:10.5281/zenodo.8068642

Wu X, Kenter T, Schade R, Kühne T, Plessl C. Computing and Compressing Electron Repulsion Integrals on FPGAs. In: 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). ; 2023:162-173. doi:10.1109/FCCM57271.2023.00026

Prouveur C, Haefele M, Kenter T, Voss N. FPGA Acceleration for HPC Supercapacitor Simulations. In: Proceedings of the Platform for Advanced Scientific Computing Conference (PASC). ACM; 2023. doi:10.1145/3592979.3593419

Meyer M, Kenter T, Plessl C. Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks. ACM Transactions on Reconfigurable Technology and Systems. Published online 2023. doi:10.1145/3576200

Opdenhövel J-O, Plessl C, Kenter T. Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation. In: Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART). ACM; 2023. doi:10.1145/3597031.3597050

Faj J, Kenter T, Faghih-Naini S, Plessl C, Aizinger V. Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes. In: Proceedings of the Platform for Advanced Scientific Computing Conference (PASC). ACM; 2023. doi:10.1145/3592979.3593407

Alt C, Kenter T, Faghih-Naini S, et al. Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline. In: Lecture Notes in Computer Science. Springer Nature Switzerland; 2023. doi:10.1007/978-3-031-32041-5_5

Karp M, Podobas A, Kenter T, et al. A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges. In: International Conference on High Performance Computing in Asia-Pacific Region. ACM; 2022. doi:10.1145/3492805.3492808

Lass M. Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations. Universität Paderborn; 2022. doi:10.17619/UNIPB/1-1281

Kühne T, Plessl C, Schade R, Schütt O. CK on the road to exascale. arXiv:220514741. Published online 2022.

Meyer M, Kenter T, Plessl C. In-depth FPGA Accelerator Performance Evaluation with Single Node Benchmarks from the HPC Challenge Benchmark Suite for Intel and Xilinx FPGAs using OpenCL. Journal of Parallel and Distributed Computing. Published online 2022. doi:10.1016/j.jpdc.2021.10.007

Schade R, Bauer C, Tamoev K, Mazur L, Plessl C, Kühne T. Parallel quantum chemistry on noisy intermediate-scale quantum computers. Phys Rev Research. 2022;4:033160. doi:10.1103/PhysRevResearch.4.033160

Gavini V, Baroni S, Blum V, et al. Roadmap on Electronic Structure Codes in the Exascale Era. arXiv:220912747. Published online 2022.

Schade R, Kenter T, Elgabarty H, et al. Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms. Parallel Computing. 2022;111. doi:10.1016/j.parco.2022.102920

Kenter T, Shambhu A, Faghih-Naini S, Aizinger V. Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA. In: Proceedings of the Platform for Advanced Scientific Computing Conference (PASC). ACM; 2021. doi:10.1145/3468267.3470617

Ramaswami A, Kenter T, Kühne T, Plessl C. Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing. In: Applied Reconfigurable Computing. Architectures, Tools, and Applications. Springer International Publishing; 2021. doi:10.1007/978-3-030-79025-7_21

Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arraysf: Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116

Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arraysf: Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116

Alhaddad S, Förstner J, Groth S, et al. HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. In: Euro-Par 2020: Parallel Processing Workshops. ; 2021. doi:10.1007/978-3-030-71593-9_15

Alhaddad S, Förstner J, Groth S, et al. The HighPerMeshes framework for numerical algorithms on unstructured grids. Concurrency and Computation: Practice and Experience. Published online 2021:e6616. doi:10.1002/cpe.6616

Menzel J, Plessl C, Kenter T. The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations. ACM Transactions on Reconfigurable Technology and Systems. 2021;15(1):1-30. doi:10.1145/3491235

Lass M, Schade R, Kühne T, Plessl C. A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CK. In: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC). IEEE Computer Society; 2020:1127-1140. doi:10.1109/SC41405.2020.00084

Rengaraj V, Lass M, Plessl C, Kühne T. Accurate Sampling with Noisy Forces from Approximate Computing. Computation. 2020;8(2). doi:10.3390/computation8020039

Kühne T, Iannuzzi M, Ben MD, et al. CK: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations. The Journal of Chemical Physics. 2020;152(19). doi:10.1063/5.0007045

Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. In: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (RC). ; 2020. doi:10.1109/h2rc51942.2020.00007

Richters D, Lass M, Walther A, Plessl C, Kühne T. A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices. Communications in Computational Physics. 2019;25(2):564-585. doi:10.4208/cicp.OA-2018-0053

Platzner M, Plessl C. FPGAs im Rechenzentrum. Informatik Spektrum. Published online 2019. doi:10.1007/s00287-019-01187-w

Gorlani P, Kenter T, Plessl C. OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2019. doi:10.1109/ICFPT47387.2019.00020

Riebler H, Vaz GF, Kenter T, Plessl C. Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL. ACM Trans Archit Code Optim (TACO). 2019;16(2):14:1–14:26. doi:10.1145/3319423

Vaz GF. Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems. Universität Paderborn; 2019.

Lass M, Mohr S, Wiebeler H, Kühne T, Plessl C. A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. In: Proc. Platform for Advanced Scientific Computing (PASC) Conference. ACM; 2018. doi:10.1145/3218176.3218231

Ramaswami A. Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn; 2018.

Riebler H, Vaz GF, Kenter T, Plessl C. Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. In: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM; 2018. doi:10.1145/3178487.3178534

Kenter T, Mahale G, Alhaddad S, et al. OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE; 2018. doi:10.1109/FCCM.2018.00037

Gadewar O. Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn; 2018.

Mertens JC, Boschmann A, Schmidt M, Plessl C. Sprint diagnostic with GPS and inertial sensor fusion. Sports Engineering. 2018;21(4):441-451. doi:10.1007/s12283-018-0291-0

Filmwala T. Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform. Universität Paderborn; 2018.

Lass M, Kühne T, Plessl C. Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots. Embedded Systems Letters. 2018;10(2):33-36. doi:10.1109/LES.2017.2760923

Riebler H, Lass M, Mittendorf R, Löcke T, Plessl C. Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2017;10(3):24:1-24:23. doi:10.1145/3053687

Kenter T, Förstner J, Plessl C. Flexible FPGA design for FDTD using OpenCL. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2017. doi:10.23919/FPL.2017.8056844

Schumacher J, Plessl C, Vandelli W. High-Throughput and Low-Latency Network Communication with NetIO. Journal of Physics: Conference Series. 2017;898. doi:10.1088/1742-6596/898/8/082003

Lass M, Leibenger D, Sorge C. Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In: Proc. 41st Conference on Local Computer Networks (LCN). IEEE; 2016. doi:10.1109/lcn.2016.11

Wüllrich G. Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment. Universität Paderborn; 2016.

Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL. In: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (RC). ; 2016.

Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop on Reconfigurable Computing (WRC). ; 2016.

Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation &; Test in Europe Conference &; Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.

Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering. 2016;55:91-111. doi:10.1016/j.compeleceng.2016.04.021

Kenter T. Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn; 2016.

Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. FPGAs for Software Programmers. Springer International Publishing; 2016:227-244. doi:10.1007/978-3-319-26408-0_13

Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: Self-Aware Computing Systems. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:10.1007/978-3-319-39675-0_8

Tölke C. Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung. Universität Paderborn; 2016.

Lass M, Kühne T, Plessl C. Using Approximate Computing in Scientific Codes. In: Workshop on Approximate Computing (AC). ; 2016.

Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). ; 2016.

Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI). IEEE; 2016:1-5. doi:10.1109/RTSI.2016.7740545

Wallaschek F. Accelerating Programmable Logic Controllers with the Use of FPGAs. Universität Paderborn; 2015.

Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z

Funke L. An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures. Universität Paderborn; 2015.

Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.

Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425

Anderson J, Borga A, Boterenbrood H, et al. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics: Conference Series. 2015;664. doi:10.1088/1742-6596/664/8/082050

Jenert T, Brahm T. How Do They Find Their Place? A Longitudinal Study of Management Students’ Attitudes and Motivations During Their First Year at Business School. In: ; 2015.

Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824

Löcke T. Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn; 2015.

Lass M. Localization and Analysis of Code Paths Suitable for Acceleration Using Approximate Computing. Paderborn: Paderborn University; 2015.

Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.

Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205

Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124

Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News. 2014;41(5):65-70. doi:10.1145/2641361.2641372

Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509

Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535

Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13

Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110

Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67

C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27

C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38

Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596

Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems. 2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001

Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.

Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394

Riebler H. Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn; 2013.

Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232

Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136

Grunzke R, Birkenheuer G, Blunk D, et al. A Data Driven Science Gateway for Computational Workflows. In: Proc. UNICORE Summit. ; 2012.

Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370

Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745

Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562. doi:10.1109/FPL.2012.6339370

Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.

Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems. 2012;36(2):110-126. doi:10.1016/j.micpro.2011.04.002

Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int Journal of Reconfigurable Computing (IJRC). Published online 2012. doi:10.1155/2012/418315

Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773

Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). ; 2012.

Plessl C, Platzner M, Agne A, Happe M, Lübbers E. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine; 2012.

Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973

Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2011:223-226. doi:10.1109/ASAP.2011.6043273