Ahmed, Qazi Arbab, et al. “MAAS: Hiding Trojans in Approximate Circuits.” The 24th International Symposium on Quality Electronic Design (ISQED’23), San Francisco, Califorina USA, 2023.

Lienen, Christian, et al. “AutonomROS: A ReconROS-Based Autonomous Driving Unit.”10.1109/irc59093.2023.00056__2023 Seventh IEEE International Conference on Robotic Computing (IRC), IEEE, 2023, doi:10.1109/irc59093.2023.00056.

Clausing, Lennart, et al. “On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks under ReconO.”https://doi.org/10.1007/978-3-031-42921-7_17__Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC), 2023, doi:https://doi.org/10.1007/978-3-031-42921-7_17.

Lienen, Christian, et al. “Mapping and Optimizing Communication in ROS 2-Based Applications on Configurable System-on-Chip Platforms.”https://doi.org/10.1145/3637843.3637846__Proceedings of the 2023 9th International Conference on Robotics and Artificial Intelligence (ICRAI), doi:https://doi.org/10.1145/3637843.3637846.

Lienen, Christian, et al. “FpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications.”10.1109/IROS55552.2023.10341921__10.1109/IROS55552.2023.10341921__Proceedings of the 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), 2023, doi:10.1109/IROS55552.2023.10341921.

Jentzsch, Felix. “Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML.”10.1109/fpl60245.2023.00066__2023 33rd International Conference on Field-Programmable Logic and Applications (FPL), IEEE, 2023, doi:10.1109/fpl60245.2023.00066.

Witschen, Linus Matthias, et al. “Search Space Characterization for Approximate Logic Synthesis .” 2022 59th ACM/IEEE Design Automation Conference (DAC).

Witschen, Linus Matthias, et al. “MUSCAT: MUS-Based Circuit Approximation Technique.” Design, Automation and Test in Europe (DATE).

Hansmeier, Tim, and Marco Platzner. “Integrating Safety Guarantees into the Learning Classifier System XCS.”10.1007/978-3-031-02462-7_25__Applications of Evolutionary Computation, EvoApplications 2022, Proceedings, vol. 13224, Springer International Publishing, 2022, pp. 386–401, doi:10.1007/978-3-031-02462-7_25.

Clausing, Lennart, and Marco Platzner. “ReconO: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support.”10.1109/ipdpsw55747.2022.00029__2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2022, pp. 120–27, doi:10.1109/ipdpsw55747.2022.00029.

Hansmeier, Tim, et al. “XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion.”10.1145/3520304.3533977__GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2022, pp. 2071–79, doi:10.1145/3520304.3533977.

Lienen, Christian, and Marco Platzner. ReconROS Executor: Event-Driven Programming of FPGA-Accelerated ROS 2 Applications. 2022.

Lienen, Christian, and Marco Platzner. Task Mapping for Hardware-Accelerated Robotics Applications Using ReconROS.

Lienen, Christian, and Marco Platzner. “Event-Driven Programming of FPGA-Accelerated ROS 2 Robotics Applications.”10.1109/DSD57027.2022.00088__2022 25th Euromicro Conference on Digital System Design (DSD), doi:10.1109/DSD57027.2022.00088.

Ahmed, Qazi Arbab, and Marco Platzner. On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs. IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022), 2022.

Awais, Muhammad, et al. “LDAX: A Learning-Based Fast Design Space Exploration Framework for Approximate Circuit Synthesis.”https://doi.org/10.1145/3453688.3461506__Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, ACM, 2021, pp. 27–32, doi:https://doi.org/10.1145/3453688.3461506.

Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient Approximate Accelerators.” Proceedings of IEEE Computer Society Annual Symposium on VLSI, IEEE, 2021, pp. 384–89.

Witschen, Linus Matthias, et al. “Timing Optimization for Virtual FPGA Configurations.”10.1007/978-3-030-79025-7_4__Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), edited by Frank Hannig et al., Springer Lecture Notes in Computer Science, doi:10.1007/978-3-030-79025-7_4.

Hansmeier, Tim. “Self-Aware Operation of Heterogeneous Compute Nodes Using the Learning Classifier System XCS.”10.1145/3468044.3468055__HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Association for Computing Machinery (ACM), 2021, doi:10.1145/3468044.3468055.

Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable Robotics Systems with ReconROS.” ArXiv:2107.07208, 2021.

Hansmeier, Tim, and Marco Platzner. “An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS.”10.1145/3449726.3463159__GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2021, pp. 1639–1647, doi:10.1145/3449726.3463159.

Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.”10.1109/vlsi-soc53125.2021.9606974__2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), 2021, doi:10.1109/vlsi-soc53125.2021.9606974.

Ahmed, Qazi Arbab, et al. “Malicious Routing: Circumventing Bitstream-Level Verification for FPGAs.”10.23919/DATE51398.2021.9474026__2021 Design, Automation &; Test in Europe Conference &; Exhibition (DATE), 2021 Design, Automation and Test in Europe Conference (DATE), 2021, doi:10.23919/DATE51398.2021.9474026.

Clausing, Lennart. “ReconO: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip.”10.1145/3468044.3468056__Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, ACM, 2021, doi:10.1145/3468044.3468056.

Ghasemzadeh Mohammadi, Hassan, et al. “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.”https://doi.org/10.1007/978-3-030-93736-2_27__https://doi.org/10.1007/978-3-030-93736-2_27__Machine Learning and Principles and Practice of Knowledge Discovery in Databases, Springer, 2021, doi:https://doi.org/10.1007/978-3-030-93736-2_27.

Guetttatfi, Zakarya, et al. “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices.” Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.

Gatica, Carlos Paiz, and Marco Platzner. “Adaptable Realization of Industrial Analytics Functions on Edge-Devices Using Reconfigurable Architectures.”10.1007/978-3-662-59084-3_9__Machine Learning for Cyber Physical Systems (ML4CPS 2017), 2020, doi:10.1007/978-3-662-59084-3_9.

Witschen, Linus Matthias, et al. “Search Space Characterization for AxC Synthesis.” Fifth Workshop on Approximate Computing (AxC 2020).

Lienen, Christian, et al. “ReconROS: Flexible Hardware Acceleration for RO Applications.” Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.

Hansmeier, Tim, et al. “An Adaption Mechanism for the Error Threshold of XCSF.”10.1145/3377929.3398106__GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2020, pp. 1756–64, doi:10.1145/3377929.3398106.

Awais, Muhammad, et al. “A Hybrid Synthesis Methodology for Approximate Circuits.”10.1145/3386263.3406952__Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, ACM, 2020, pp. 421–26, doi:10.1145/3386263.3406952.

Hansmeier, Tim, et al. “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold.”10.1145/3377929.3389968__GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2020, pp. 125–26, doi:10.1145/3377929.3389968.

Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes.”10.1109/ipdpsw50202.2020.00012__2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020, doi:10.1109/ipdpsw50202.2020.00012.

Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes.”10.1109/IPDPSW50202.2020.00012__2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020, pp. 6–16, doi:10.1109/IPDPSW50202.2020.00012.

Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019).

Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.”10.1145/3299874.3317998__Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19, ACM, 2019, doi:10.1145/3299874.3317998.

Ho, Nam, et al. “Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor.” World Congress on Nature and Biologically Inspired Computing (NaBIC), Springer, 2019.

Guettatfi, Zakarya, et al. “An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware.”10.1109/ipdpsw.2019.00027__2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2019, doi:10.1109/ipdpsw.2019.00027.

Ahmed, Qazi Arbab, et al. “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan.”10.1007/978-3-030-17227-5_10__Applied Reconfigurable Computing, edited by Christian Hochberger et al., vol. 11444, Springer International Publishing, 2019, pp. 127–36, doi:10.1007/978-3-030-17227-5_10.

Lösch, Achim, et al. “Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes.”10.1007/978-3-319-77610-1_6__Proceedings of the International Conference on Architecture of Computing Systems (ARCS), vol. 10793, Springer International Publishing, 2018, pp. 73–84, doi:10.1007/978-3-319-77610-1_6.

Hansmeier, Tim, et al. “An FPGA/HMC-Based Accelerator for Resolution Proof Checking.”10.1007/978-3-319-78890-6_13__ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, vol. 10824, Springer International Publishing, 2018, pp. 153–65, doi:10.1007/978-3-319-78890-6_13.

Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Third Workshop on Approximate Computing (AxC 2018).

Witschen, Linus Matthias, et al. “Making the Case for Proof-Carrying Approximate Circuits.” 4th Workshop On Approximate Computing (WAPCO 2018), 2018.

Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.”10.1109/asap.2018.8445098__2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), IEEE, 2018, doi:10.1109/asap.2018.8445098.

Awais, Muhammad, et al. “An MCTS-Based Framework for Synthesis of Approximate Circuits.”10.1109/VLSI-SoC.2018.8645026__26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–24, doi:10.1109/VLSI-SoC.2018.8645026.

Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.”10.1109/ASAP.2017.7995272__Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017, doi:10.1109/ASAP.2017.7995272.

Boschmann, Alexander, et al. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric Prosthesis Controller.”10.23919/DATE.2017.7927137__Design, Automation and Test in Europe (DATE), 2017, doi:10.23919/DATE.2017.7927137.

Ho, Nam, et al. “Accurate Private/Shared Classification of Memory Accesses: A Run-Time Analysis System for the LEON3 Multi-Core Processor.”10.23919/DATE.2017.7927096__Proc. Design, Automation and Test in Europe Conf. (DATE), 2017, doi:10.23919/DATE.2017.7927096.

Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.”10.1109/FPT.2017.8280144__2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–18, doi:10.1109/FPT.2017.8280144.

Kaufmann, Paul, and Roman Kalkreuth. “Parametrizing Cartesian Genetic Programming: An Empirical Study.”10.1007/978-3-319-67190-1_26__KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI, Springer International Publishing, 2017, doi:10.1007/978-3-319-67190-1_26.

Kaufmann, Paul, et al. “Evaluation Methodology for Complex Non-Deterministic Functions: A Case Study in Metaheuristic Optimization of Caches.”10.1109/AHS.2017.8046380__Adaptive Hardware and Systems (AHS), IEEE, 2017, doi:10.1109/AHS.2017.8046380.

Kaufmann, Paul, and Roman Kalkreuth. “An Empirical Study on the Parametrization of Cartesian Genetic Programming.”10.1145/3067695.3075980__Genetic and Evolutionary Computation (GECCO), Compendium, ACM, 2017, doi:10.1145/3067695.3075980.

Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.”10.1109/ReCoSoC.2017.8016147__12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8, doi:10.1109/ReCoSoC.2017.8016147.

Ghribi, Ines, et al. “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems.”10.1007/978-3-319-62569-0_8__Communications in Computer and Information Science, Springer , 2017, doi:10.1007/978-3-319-62569-0_8.

Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.”10.1109/reconfig.2015.7393312__2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312.

Anwer, Jahanzeb, and Marco Platzner. “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs.”10.1109/DSD.2016.35__Euromicro Conference on Digital System Design (DSD), 2016, doi:10.1109/DSD.2016.35.

Boschmann, Alexander, et al. “A Novel Immersive Augmented Reality System for Prosthesis Training and Assessment.” Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.

Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level.”10.1109/ReConFig.2016.7857193__Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8, doi:10.1109/ReConFig.2016.7857193.

Ghribi, Ines, et al. “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.

Ghribi, Ines, et al. “New Co-Design Methodology for Real-Time Embedded Systems.” Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–95.

Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.”10.1109/reconfig.2015.7393312__2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312.

Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” Computer and Games, 2016.

Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” IEEE Computational Intelligence and Games, 2016.

Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.”10.1109/ReCoSoC.2016.7533910__Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8, doi:10.1109/ReCoSoC.2016.7533910.

Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation &; Test in Europe Conference &; Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17.

Wiersema, Tobias, et al. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.”10.1007/978-3-319-16214-0_32__Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372, doi:10.1007/978-3-319-16214-0_32.

Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.”10.1109/AHS.2015.7231178__Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178.

Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–16.

Meisner, Sebastian, and Marco Platzner. “Comparison of Thread Signatures for Error Detection in Hybrid Multi-Cores.”10.1109/FPT.2015.7393153__Field Programmable Technology (FPT), 2015 International Conference On, 2015, pp. 212–15, doi:10.1109/FPT.2015.7393153.

H.W. Leong, Philip, et al. “Significant Papers from the First 25 Years of the FPL Conference.”10.1109/FPL.2015.7293747__Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, pp. 1–3, doi:10.1109/FPL.2015.7293747.

Ghribi, Ines, et al. “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software.” Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015.

Ghasemzadeh Mohammadi, Hassan, et al. “On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.”10.1109/ISVLSI.2015.13__2015 IEEE Computer Society Annual Symposium on VLSI, IEEE, 2015, pp. 491–96, doi:10.1109/ISVLSI.2015.13.

Ghasemzadeh Mohammadi, Hassan, et al. “Fault Modeling in Controllable Polarity Silicon Nanowire Circuits.”10.7873/DATE.2015.0428__Proceedings of the 2015 Design, Automation &; Test in Europe Conference \'26; Exhibition, EDA Consortium, 2015, pp. 453–58, doi:10.7873/DATE.2015.0428.

Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.”10.1109/FPL.2015.7293994__25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, doi:10.1109/FPL.2015.7293994.

Graf, Tobias, and Marco Platzner. “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning.”10.1007/978-3-319-27992-3_1__Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, Springer International Publishing, 2015, pp. 1–11, doi:10.1007/978-3-319-27992-3_1.

Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.

Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.”10.1145/2675743.2771824__Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.

Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.”10.7873/DATE.2015.1124__Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124.

Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-Cores for Error Detection.”10.1007/978-3-319-05960-0_30__Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), edited by Diana Goehringer et al., Springer, 2014, pp. 283–90, doi:10.1007/978-3-319-05960-0_30.

Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.”10.1007/978-3-319-09165-5_2__Proc. Conf. on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2.

Wiersema, Tobias, et al. “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring.”10.1109/FPT.2014.7082771__Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–74, doi:10.1109/FPT.2014.7082771.

Jakobs, Marie-Christine, et al. “Integrating Software and Hardware Verification.”10.1007/978-3-319-10181-1_19__Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), edited by Elvira Albert and Emil Sekerinski, 2014, pp. 307–22, doi:10.1007/978-3-319-10181-1_19.

Wiersema, Tobias, et al. “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS Meets ZUMA.”10.1109/ReConFig.2014.7032514__Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6, doi:10.1109/ReConFig.2014.7032514.

Anwer, Jahanzeb, et al. “FPGA Redundancy Configurations: An Automated Design Space Exploration.”10.1109/IPDPSW.2014.37__Reconfigurable Architectures Workshop (RAW), 2014, doi:10.1109/IPDPSW.2014.37.

Boschmann, Alexander, and Marco Platzner. “A Computer Vision-Based Approach to High Density EMG Pattern Recognition Using Structural Similarity.” Proc. MyoElectric Controls Symposium (MEC), 2014.

Boschmann, Alexander, and Marco Platzner. “Towards Robust HD EMG Pattern Recognition: Reducing Electrode Displacement Effect Using Structural Similarity.” Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.

Glette, Kyrre, and Paul Kaufmann. “Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System.” IEEE Congress on Evolutionary Computation (CEC), 2014.

Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.”10.1109/FPL.2014.6927437__24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4, doi:10.1109/FPL.2014.6927437.

Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.”10.1109/ICES.2014.7008719__2014 IEEE Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37, doi:10.1109/ICES.2014.7008719.

Shen, Cong, et al. “Optimizing the Generator Start-up Sequence After a Power System Blackout.” IEEE Power and Energy Society General Meeting (IEEE GM), 2014.

Shen, Cong, et al. “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm.” Power Systems Computation Conference (PSCC), IEEE, 2014.

Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant Circuit Structures on FPGAs.”10.1109/DFT.2014.6962108__IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–84, doi:10.1109/DFT.2014.6962108.

Ghasemzadeh Mohammadi, Hassan, et al. “Fast Process Variation Analysis in Nano-Scaled Technologies Using Column-Wise Sparse Parameter Selection.”10.1109/NANOARCH.2014.6880479__2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163–68, doi:10.1109/NANOARCH.2014.6880479.

Graf, Tobias, and Marco Platzner. “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go.”10.1109/CIG.2014.6932863__2014 IEEE Conference on Computational Intelligence and Games, 2014, pp. 1–8, doi:10.1109/CIG.2014.6932863.

Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.”10.1007/978-3-319-05960-0_13__Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.

Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.”10.1109/FCCM.2014.67__Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.

C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.”10.1109/ISPA.2014.27__Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.

Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.”10.1109/ReConFig.2014.7032509__Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.

Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.”10.1109/ReConFig.2014.7032535__Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.

C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.”10.1007/978-3-319-05960-0_38__Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.