Parametrizing Cartesian Genetic Programming: An Empirical Study
P. Kaufmann, R. Kalkreuth, in: KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI, Springer International Publishing, 2017.
LibreCat: /record/10760
DOI: 10.1007/978-3-319-67190-1_26

Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches
P. Kaufmann, N. Ho, M. Platzner, in: Adaptive Hardware and Systems (AHS), IEEE, 2017.
LibreCat: /record/10761
DOI: 10.1109/AHS.2017.8046380

An Empirical Study on the Parametrization of Cartesian Genetic Programming
P. Kaufmann, R. Kalkreuth, in: Genetic and Evolutionary Computation (GECCO), Compendium, ACM, 2017.
LibreCat: /record/10762
DOI: 10.1145/3067695.3075980

Computational self-awareness as design approach for visual sensor nodes
Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.
LibreCat: /record/10780
DOI: 10.1109/ReCoSoC.2017.8016147

I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems
I. Ghribi, R.B. Abdallah, M. Khalgui, M. Platzner, in: Communications in Computer and Information Science, Springer , Cham, 2017.
LibreCat: /record/14893
DOI: 10.1007/978-3-319-62569-0_8

FPGA-based acceleration of high density myoelectric signal processing
A. Boschmann, A. Agne, L. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.
LibreCat: /record/5812
DOI: 10.1109/reconfig.2015.7393312

Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs
J. Anwer, M. Platzner, in: Euromicro Conference on Digital System Design (DSD), 2016.
LibreCat: /record/10622
DOI: 10.1109/DSD.2016.35

A novel immersive augmented reality system for prosthesis training and assessment
A. Boschmann, S. Dosen, A. Werner, A. Raies, D. Farina, in: Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.
LibreCat: /record/10631

Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level
S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8.
LibreCat: /record/10712
DOI: 10.1109/ReConFig.2016.7857193

RCo-Design: New Visual Environment for Reconfigurable Embedded Systems
I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.
LibreCat: /record/10766

New Co-design Methodology for Real-time Embedded Systems
I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–195.
LibreCat: /record/10768

FPGA-based acceleration of high density myoelectric signal processing
A. Boschmann, A. Agne, L.M. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.
LibreCat: /record/15873
DOI: 10.1109/reconfig.2015.7393312

Using Deep Convolutional Neural Networks in Monte Carlo Tree Search
T. Graf, M. Platzner, in: Computer and Games, 2016.
LibreCat: /record/13151

Monte-Carlo Simulation Balancing Revisited
T. Graf, M. Platzner, in: IEEE Computational Intelligence and Games, 2016.
LibreCat: /record/13152

Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware
T. Wiersema, M. Platzner, in: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8.
LibreCat: /record/132
DOI: 10.1109/ReCoSoC.2016.7533910

Performance-centric scheduling with task migration for a heterogeneous compute node in the data center
A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation &; Test in Europe Conference &; Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.
LibreCat: /record/168

On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach
T. Wiersema, S. Wu, M. Platzner, in: Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372.
LibreCat: /record/269
DOI: 10.1007/978-3-319-16214-0_32

Microarchitectural optimization by means of reconfigurable and evolvable cache mappings
N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.
LibreCat: /record/10673
DOI: 10.1109/AHS.2015.7231178

Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing
P. Kaufmann, C. Shen, in: Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–416.
LibreCat: /record/10693

Comparison of thread signatures for error detection in hybrid multi-cores
S. Meisner, M. Platzner, in: Field Programmable Technology (FPT), 2015 International Conference On, 2015, pp. 212–215.
LibreCat: /record/10711
DOI: 10.1109/FPT.2015.7393153

Significant papers from the first 25 years of the FPL conference
P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna, T. Rissa, C. Silvano, H. So, Y. Wang, in: Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, pp. 1–3.
LibreCat: /record/10765
DOI: 10.1109/FPL.2015.7293747

New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software
I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015.
LibreCat: /record/10767

On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors
H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, M.S. Reorda, in: 2015 IEEE Computer Society Annual Symposium on VLSI, IEEE, 2015, pp. 491–496.
LibreCat: /record/10771
DOI: 10.1109/ISVLSI.2015.13

Fault modeling in controllable polarity silicon nanowire circuits
H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, in: Proceedings of the 2015 Design, Automation &; Test in Europe Conference \'26; Exhibition, EDA Consortium, 2015, pp. 453–458.
LibreCat: /record/10772
DOI: 10.7873/DATE.2015.0428

Over effective hard real-time hardware tasks scheduling and allocation
Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015.
LibreCat: /record/10779
DOI: 10.1109/FPL.2015.7293994

Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning
T. Graf, M. Platzner, in: Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, Springer International Publishing, 2015, pp. 1–11.
LibreCat: /record/13153
DOI: 10.1007/978-3-319-27992-3_1

Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores
M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.
LibreCat: /record/303
arXiv: 1412.3906

Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm
J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.
LibreCat: /record/1773
DOI: 10.1145/2675743.2771824

Transparent offloading of computational hotspots from binary code to Xeon Phi
M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.
LibreCat: /record/238
DOI: 10.7873/DATE.2015.1124

Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection
S. Meisner, M. Platzner, in: D. Goehringer, M. Santambrogio, J.P. Cardoso, K. Bertels (Eds.), Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), Springer, 2014, pp. 283–290.
LibreCat: /record/347
DOI: 10.1007/978-3-319-05960-0_30

On Semeai Detection in Monte-Carlo Go
T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, Switzerland, 2014, pp. 14–25.
LibreCat: /record/1782
DOI: 10.1007/978-3-319-09165-5_2

Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring
T. Wiersema, S. Drzevitzky, M. Platzner, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–174.
LibreCat: /record/399
DOI: 10.1109/FPT.2014.7082771

Integrating Software and Hardware Verification
M.-C. Jakobs, M. Platzner, T. Wiersema, H. Wehrheim, in: E. Albert, E. Sekerinski (Eds.), Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), 2014, pp. 307–322.
LibreCat: /record/408
DOI: 10.1007/978-3-319-10181-1_19

Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA
T. Wiersema, A. Bockhorn, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.
LibreCat: /record/433
DOI: 10.1109/ReConFig.2014.7032514

FPGA Redundancy Configurations: An Automated Design Space Exploration
J. Anwer, M. Platzner, S. Meisner, in: Reconfigurable Architectures Workshop (RAW), 2014.
LibreCat: /record/10621
DOI: 10.1109/IPDPSW.2014.37

A computer vision-based approach to high density EMG pattern recognition using structural similarity
A. Boschmann, M. Platzner, in: Proc. MyoElectric Controls Symposium (MEC), 2014.
LibreCat: /record/10632

Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity
A. Boschmann, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.
LibreCat: /record/10633

Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System
K. Glette, P. Kaufmann, in: IEEE Congress on Evolutionary Computation (CEC), 2014.
LibreCat: /record/10654

A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms
N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.
LibreCat: /record/10674
DOI: 10.1109/FPL.2014.6927437

Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure
N. Ho, P. Kaufmann, M. Platzner, in: 2014 IEEE Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.
LibreCat: /record/10677
DOI: 10.1109/ICES.2014.7008719

Optimizing the Generator Start-up Sequence After a Power System Blackout
C. Shen, P. Kaufmann, M. Braun, in: IEEE Power and Energy Society General Meeting (IEEE GM), 2014.
LibreCat: /record/10738

A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm
C. Shen, P. Kaufmann, M. Braun, in: Power Systems Computation Conference (PSCC), IEEE, 2014.
LibreCat: /record/10739

Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs
J. Anwer, M. Platzner, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–184.
LibreCat: /record/10764
DOI: 10.1109/DFT.2014.6962108

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection
H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163–168.
LibreCat: /record/10773
DOI: 10.1109/NANOARCH.2014.6880479

Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go
T. Graf, M. Platzner, in: 2014 IEEE Conference on Computational Intelligence and Games, 2014, pp. 1–8.
LibreCat: /record/13154
DOI: 10.1109/CIG.2014.6932863

Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer
T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.
LibreCat: /record/388
DOI: 10.1007/978-3-319-05960-0_13

Reconstructing AES Key Schedules from Decayed Memory with FPGAs
H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.
LibreCat: /record/377
DOI: 10.1109/FCCM.2014.67

Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach
G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.
LibreCat: /record/1778
DOI: 10.1109/ISPA.2014.27

Deferring Accelerator Offloading Decisions to Application Runtime
G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.
LibreCat: /record/439
DOI: 10.1109/ReConFig.2014.7032509

Kernel-Centric Acceleration of High Accuracy Stereo-Matching
T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.
LibreCat: /record/406
DOI: 10.1109/ReConFig.2014.7032535