Awais M, Ghasemzadeh Mohammadi H, Platzner M. DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing. In: To Apear in IEEE ISVLSI 2024. ; 2024.
LibreCat: /record/54468

Ahmed QA, Awais M, Platzner M. MAAS: Hiding Trojans in Approximate Circuits. In: The 24th International Symposium on Quality Electronic Design (ISQED’23), San Francisco, Califorina USA. ; 2023.
LibreCat: /record/44194

Lienen C, Brede M, Karger D, et al. AutonomROS: A ReconROS-based Autonomous Driving Unit. In: 2023 Seventh IEEE International Conference on Robotic Computing (IRC). IEEE; 2023. doi:10.1109/irc59093.2023.00056
LibreCat: /record/53794
DOI: 10.1109/irc59093.2023.00056

Clausing L, Guetattfi Z, Kaufmann P, Lienen C, Platzner M. On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconO. In: Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC). ; 2023. doi:https://doi.org/10.1007/978-3-031-42921-7_17
LibreCat: /record/45913
DOI: https://doi.org/10.1007/978-3-031-42921-7_17

Lienen C, Nowosad AP, Platzner M. Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms. In: Proceedings of the 2023 9th International Conference on Robotics and Artificial Intelligence (ICRAI). doi:https://doi.org/10.1145/3637843.3637846
LibreCat: /record/46229
DOI: https://doi.org/10.1145/3637843.3637846

Lienen C, Middeke SH, Platzner M. fpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications. In: 10.1109/IROS55552.2023.10341921__Proceedings of the 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS). ; 2023. doi:10.1109/IROS55552.2023.10341921
LibreCat: /record/43048
DOI: 10.1109/IROS55552.2023.10341921

Jentzsch F. Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML. In: 2023 33rd International Conference on Field-Programmable Logic and Applications (FPL). IEEE; 2023. doi:10.1109/fpl60245.2023.00066
LibreCat: /record/53435
DOI: 10.1109/fpl60245.2023.00066

Witschen LM, Wiersema T, Reuter LD, Platzner M. Search Space Characterization for Approximate Logic Synthesis . In: 2022 59th ACM/IEEE Design Automation Conference (DAC).
LibreCat: /record/29945

Witschen LM, Wiersema T, Artmann M, Platzner M. MUSCAT: MUS-based Circuit Approximation Technique. In: Design, Automation and Test in Europe (DATE).
LibreCat: /record/29865

Hansmeier T, Platzner M. Integrating Safety Guarantees into the Learning Classifier System XCS. In: Applications of Evolutionary Computation, EvoApplications 2022, Proceedings. Vol 13224. Lecture Notes in Computer Science. Springer International Publishing; 2022:386-401. doi:10.1007/978-3-031-02462-7_25
LibreCat: /record/30971
DOI: 10.1007/978-3-031-02462-7_25

Clausing L, Platzner M. ReconO: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support. In: 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE; 2022:120-127. doi:10.1109/ipdpsw55747.2022.00029
LibreCat: /record/32855
DOI: 10.1109/ipdpsw55747.2022.00029

Hansmeier T, Brede M, Platzner M. XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion. In: GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion. Association for Computing Machinery (ACM); 2022:2071-2079. doi:10.1145/3520304.3533977
LibreCat: /record/33253
DOI: 10.1145/3520304.3533977

Lienen C, Platzner M. ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications. Published online 2022.
LibreCat: /record/29541

Lienen C, Platzner M. Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS.
LibreCat: /record/34007

Lienen C, Platzner M. Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications. In: 2022 25th Euromicro Conference on Digital System Design (DSD). doi:10.1109/DSD57027.2022.00088
LibreCat: /record/34005
DOI: 10.1109/DSD57027.2022.00088

Ahmed QA, Platzner M. On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022); 2022.
LibreCat: /record/32342

Awais M, Ghasemzadeh Mohammadi H, Platzner M. LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis. In: Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021. ACM; 2021:27-32. doi:https://doi.org/10.1145/3453688.3461506
LibreCat: /record/21610
DOI: https://doi.org/10.1145/3453688.3461506

Awais M, Platzner M. MCTS-Based Synthesis Towards Efficient Approximate Accelerators. In: Proceedings of IEEE Computer Society Annual Symposium on VLSI. IEEE; 2021:384-389.
LibreCat: /record/22309

Witschen LM, Wiersema T, Raeisi Nafchi M, Bockhorn A, Platzner M. Timing Optimization for Virtual FPGA Configurations. In: Hannig F, Derrien S, Diniz P, Chillet D, eds. Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21). Reconfigurable Computing: Architectures, Tools, and Applications. Springer Lecture Notes in Computer Science. doi:10.1007/978-3-030-79025-7_4
LibreCat: /record/21953
DOI: 10.1007/978-3-030-79025-7_4

Hansmeier T. Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS. In: HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. Association for Computing Machinery (ACM); 2021. doi:10.1145/3468044.3468055
LibreCat: /record/29137
DOI: 10.1145/3468044.3468055

Lienen C, Platzner M. Design of Distributed Reconfigurable Robotics Systems with ReconROS. arXiv:210707208. Published online 2021.
LibreCat: /record/22764

Hansmeier T, Platzner M. An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS. In: GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion. Association for Computing Machinery (ACM); 2021:1639–1647. doi:10.1145/3449726.3463159
LibreCat: /record/21813
DOI: 10.1145/3449726.3463159

Ahmed QA. Hardware Trojans in Reconfigurable Computing. In: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC). ; 2021. doi:10.1109/vlsi-soc53125.2021.9606974
LibreCat: /record/29138
DOI: 10.1109/vlsi-soc53125.2021.9606974

Ahmed QA, Wiersema T, Platzner M. Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. In: 2021 Design, Automation &; Test in Europe Conference &; Exhibition (DATE). 2021 Design, Automation and Test in Europe Conference (DATE); 2021. doi:10.23919/DATE51398.2021.9474026
LibreCat: /record/20681
DOI: 10.23919/DATE51398.2021.9474026

Clausing L. ReconO: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip. In: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ACM; 2021. doi:10.1145/3468044.3468056
LibreCat: /record/30909
DOI: 10.1145/3468044.3468056

Ghasemzadeh Mohammadi H, Jentzsch F, Kuschel M, et al. FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics. In: https://doi.org/10.1007/978-3-030-93736-2_27__Machine Learning and Principles and Practice of Knowledge Discovery in Databases. Springer; 2021. doi:https://doi.org/10.1007/978-3-030-93736-2_27
LibreCat: /record/30908
DOI: https://doi.org/10.1007/978-3-030-93736-2_27

Guetttatfi Z, Kaufmann P, Platzner M. Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices. In: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC). ; 2020.
LibreCat: /record/3583

Gatica CP, Platzner M. Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures. In: Machine Learning for Cyber Physical Systems (ML4CPS 2017). Berlin, Heidelberg; 2020. doi:10.1007/978-3-662-59084-3_9
LibreCat: /record/21584
DOI: 10.1007/978-3-662-59084-3_9

Witschen LM, Wiersema T, Platzner M. Search Space Characterization for AxC Synthesis. Fifth Workshop on Approximate Computing (AxC 2020).
LibreCat: /record/20748

Lienen C, Platzner M, Rinner B. ReconROS: Flexible Hardware Acceleration for RO Applications. In: Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT). ; 2020.
LibreCat: /record/20750

Hansmeier T, Kaufmann P, Platzner M. An Adaption Mechanism for the Error Threshold of XCSF. In: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion. Association for Computing Machinery (ACM); 2020:1756-1764. doi:10.1145/3377929.3398106
LibreCat: /record/17063
DOI: 10.1145/3377929.3398106

Awais M, Ghasemzadeh Mohammadi H, Platzner M. A Hybrid Synthesis Methodology for Approximate Circuits. In: Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020. ACM; 2020:421-426. doi:10.1145/3386263.3406952
LibreCat: /record/16213
DOI: 10.1145/3386263.3406952

Hansmeier T, Kaufmann P, Platzner M. Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold. In: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion. New York, NY, United States: Association for Computing Machinery (ACM); 2020:125-126. doi:10.1145/3377929.3389968
LibreCat: /record/16363
DOI: 10.1145/3377929.3389968

Lösch A, Platzner M. MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes. In: 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). ; 2020. doi:10.1109/ipdpsw50202.2020.00012
LibreCat: /record/20838
DOI: 10.1109/ipdpsw50202.2020.00012

Lösch A, Platzner M. MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes. In: 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). ; 2020:6-16. doi:10.1109/IPDPSW50202.2020.00012
LibreCat: /record/35152
DOI: 10.1109/IPDPSW50202.2020.00012

Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop on Approximate Computing (AxC 2019).
LibreCat: /record/16853

Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. In: Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19. New York, NY, USA: ACM; 2019. doi:10.1145/3299874.3317998
LibreCat: /record/10577
DOI: 10.1145/3299874.3317998

Ho N, Kaufmann P, Platzner M. Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor. In: World Congress on Nature and Biologically Inspired Computing (NaBIC). Advances in Nature and Biologically Inspired Computing. Springer; 2019.
LibreCat: /record/15422

Guettatfi Z, Platzner M, Kermia O, Khouas A. An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware. In: 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE; 2019. doi:10.1109/ipdpsw.2019.00027
LibreCat: /record/31067
DOI: 10.1109/ipdpsw.2019.00027

Ahmed QA, Wiersema T, Platzner M. Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan. In: Hochberger C, Nelson B, Koch A, Woods R, Diniz P, eds. Applied Reconfigurable Computing. Vol 11444. Lecture Notes in Computer Science. Springer International Publishing; 2019:127-136. doi:10.1007/978-3-030-17227-5_10
LibreCat: /record/9913
DOI: 10.1007/978-3-030-17227-5_10

Lösch A, Wiens A, Platzner M. Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes. In: Proceedings of the International Conference on Architecture of Computing Systems (ARCS). Vol 10793. Lecture Notes in Computer Science. Cham: Springer International Publishing; 2018:73-84. doi:10.1007/978-3-319-77610-1_6
LibreCat: /record/3362
DOI: 10.1007/978-3-319-77610-1_6

Hansmeier T, Platzner M, Andrews D. An FPGA/HMC-Based Accelerator for Resolution Proof Checking. In: ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications. Vol 10824. Lecture Notes in Computer Science. Springer International Publishing; 2018:153-165. doi:10.1007/978-3-319-78890-6_13
LibreCat: /record/3373
DOI: 10.1007/978-3-319-78890-6_13

Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Third Workshop on Approximate Computing (AxC 2018).
LibreCat: /record/3586

Witschen LM, Wiersema T, Platzner M. Making the Case for Proof-carrying Approximate Circuits. 4th Workshop On Approximate Computing (WAPCO 2018). 2018.
LibreCat: /record/1165

Lösch A, Platzner M. A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. In: 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP). IEEE; 2018. doi:10.1109/asap.2018.8445098
LibreCat: /record/5547
DOI: 10.1109/asap.2018.8445098

Awais M, Ghasemzadeh Mohammadi H, Platzner M. An MCTS-based Framework for Synthesis of Approximate Circuits. In: 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). ; 2018:219-224. doi:10.1109/VLSI-SoC.2018.8645026
LibreCat: /record/10598
DOI: 10.1109/VLSI-SoC.2018.8645026

Lösch A, Platzner M. reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In: Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP). ; 2017. doi:10.1109/ASAP.2017.7995272
LibreCat: /record/65
DOI: 10.1109/ASAP.2017.7995272

Boschmann A, Thombansen G, Witschen LM, Wiens A, Platzner M. A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In: Design, Automation and Test in Europe (DATE). ; 2017. doi:10.23919/DATE.2017.7927137
LibreCat: /record/10630
DOI: 10.23919/DATE.2017.7927137

Ho N, Ashraf II, Kaufmann P, Platzner M. Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor. In: Proc. Design, Automation and Test in Europe Conf. (DATE). ; 2017. doi:10.23919/DATE.2017.7927096
LibreCat: /record/10672
DOI: 10.23919/DATE.2017.7927096

Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144
LibreCat: /record/10676
DOI: 10.1109/FPT.2017.8280144