M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing,” presented at the IEEE Computer Society Annual Symposium on VLSI, Knoxville, Tennessee, USA, 2024.
LibreCat: /record/54468

Q. A. Ahmed, M. Awais, and M. Platzner, “MAAS: Hiding Trojans in Approximate Circuits,” presented at the The 24th International Symposium on Quality Electronic Design (ISQED’23), San Fransico CA 94023-0607, USA, 2023.
LibreCat: /record/44194

C. Lienen et al., “AutonomROS: A ReconROS-based Autonomous Driving Unit,”10.1109/irc59093.2023.00056__2023, doi:10.1109/irc59093.2023.00056 .
LibreCat: /record/53794
DOI: 10.1109/irc59093.2023.00056

L. Clausing, Z. Guetattfi, P. Kaufmann, C. Lienen, and M. Platzner, “On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconO,”https://doi.org/10.1007/978-3-031-42921-7_17__2023, doi:https://doi.org/10.1007/978-3-031-42921-7_17 .
LibreCat: /record/45913
DOI: https://doi.org/10.1007/978-3-031-42921-7_17

C. Lienen, A. P. Nowosad, and M. Platzner, “Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms,”https://doi.org/10.1145/3637843.3637846__doi:https://doi.org/10.1145/3637843.3637846 .
LibreCat: /record/46229
DOI: https://doi.org/10.1145/3637843.3637846

C. Lienen, S. H. Middeke, and M. Platzner, pgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications,”10.1109/IROS55552.2023.10341921__2023, doi:10.1109/IROS55552.2023.10341921 .
LibreCat: /record/43048
DOI: 10.1109/IROS55552.2023.10341921

F. Jentzsch, “Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML,”10.1109/fpl60245.2023.00066__2023, doi:10.1109/fpl60245.2023.00066 .
LibreCat: /record/53435
DOI: 10.1109/fpl60245.2023.00066

L. M. Witschen, T. Wiersema, L. D. Reuter, and M. Platzner, “Search Space Characterization for Approximate Logic Synthesis ,” presented at the 2022 59th ACM/IEEE Design Automation Conference (DAC), San Francisco, USA.
LibreCat: /record/29945

L. M. Witschen, T. Wiersema, M. Artmann, and M. Platzner, “MUSCAT: MUS-based Circuit Approximation Technique,” presented at the Design, Automation and Test in Europe (DATE), Online.
LibreCat: /record/29865

T. Hansmeier and M. Platzner, “Integrating Safety Guarantees into the Learning Classifier System XCS,”10.1007/978-3-031-02462-7_25__in Applications of Evolutionary Computation, EvoApplications 2022, Proceedings, Madrid, 2022, vol. 13224, pp. 386–401, doi:10.1007/978-3-031-02462-7_25 .
LibreCat: /record/30971
DOI: 10.1007/978-3-031-02462-7_25

L. Clausing and M. Platzner, “ReconO: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support,”10.1109/ipdpsw55747.2022.00029__in 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW),10.1109/ipdpsw55747.2022.00029__Lyon, France, 2022, pp. 120–127, doi:10.1109/ipdpsw55747.2022.00029 .
LibreCat: /record/32855
DOI: 10.1109/ipdpsw55747.2022.00029

T. Hansmeier, M. Brede, and M. Platzner, “XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion,”10.1145/3520304.3533977__in GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Boston, MA, USA, 2022, pp. 2071–2079, doi:10.1145/3520304.3533977 .
LibreCat: /record/33253
DOI: 10.1145/3520304.3533977

C. Lienen and M. Platzner, “ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications.” 2022.
LibreCat: /record/29541

C. Lienen and M. Platzner, “Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS,” presented at the 2022 Sixth IEEE International Conference on Robotic Computing (IRC) , Neaples, Italy.
LibreCat: /record/34007

C. Lienen and M. Platzner, “Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications,”10.1109/DSD57027.2022.00088__presented at the 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Gran Canaria, Spain, doi:10.1109/DSD57027.2022.00088 .
LibreCat: /record/34005
DOI: 10.1109/DSD57027.2022.00088

Q. A. Ahmed and M. Platzner, “On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs,” presented at the IEEE Computer Society Annual Symposium on VLSI Aliathon Resort, Pafos, Cyprus, 2022.
LibreCat: /record/32342

M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis,” in Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, Virtual, 2021, pp. 27–32.
LibreCat: /record/21610
DOI: https://doi.org/10.1145/3453688.3461506

M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate Accelerators,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Tampa, Florida USA (Virtual), 2021, pp. 384–389.
LibreCat: /record/22309

L. M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, and M. Platzner, “Timing Optimization for Virtual FPGA Configurations,”10.1007/978-3-030-79025-7_4__in Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Virtual conference, doi:10.1007/978-3-030-79025-7_4 .
LibreCat: /record/21953
DOI: 10.1007/978-3-030-79025-7_4

T. Hansmeier, “Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS,”10.1145/3468044.3468055__presented at the International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), Online, 2021, doi:10.1145/3468044.3468055 .
LibreCat: /record/29137
DOI: 10.1145/3468044.3468055

C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,” arXiv:2107.07208. 2021.
LibreCat: /record/22764

T. Hansmeier and M. Platzner, “An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS,”10.1145/3449726.3463159__in GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Lille, France, 2021, pp. 1639–1647, doi:10.1145/3449726.3463159 .
LibreCat: /record/21813
DOI: 10.1145/3449726.3463159

Q. A. Ahmed, “Hardware Trojans in Reconfigurable Computing,”10.1109/vlsi-soc53125.2021.9606974__2021, doi:10.1109/vlsi-soc53125.2021.9606974 .
LibreCat: /record/29138
DOI: 10.1109/vlsi-soc53125.2021.9606974

Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing Bitstream-level Verification for FPGAs,”10.23919/DATE51398.2021.9474026__presented at the Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France, 2021, doi:10.23919/DATE51398.2021.9474026 .
LibreCat: /record/20681
DOI: 10.23919/DATE51398.2021.9474026

L. Clausing, “ReconO: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip,”10.1145/3468044.3468056__2021, doi:10.1145/3468044.3468056 .
LibreCat: /record/30909
DOI: 10.1145/3468044.3468056

H. Ghasemzadeh Mohammadi et al., “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics,”https://doi.org/10.1007/978-3-030-93736-2_27__2021, doi:https://doi.org/10.1007/978-3-030-93736-2_27 .
LibreCat: /record/30908
DOI: https://doi.org/10.1007/978-3-030-93736-2_27

Z.  Guetttatfi, P. Kaufmann, and M. Platzner, “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices,” in Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.
LibreCat: /record/3583

C. P. Gatica and M. Platzner, “Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures,” in Machine Learning for Cyber Physical Systems (ML4CPS 2017), 2020.
LibreCat: /record/21584
DOI: 10.1007/978-3-662-59084-3_9

L. M. Witschen, T. Wiersema, and M. Platzner, “Search Space Characterization for AxC Synthesis,” Fifth Workshop on Approximate Computing (AxC 2020). .
LibreCat: /record/20748

C. Lienen, M. Platzner, and B. Rinner, “ReconROS: Flexible Hardware Acceleration for RO Applications,” in Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.
LibreCat: /record/20750

T. Hansmeier, P. Kaufmann, and M. Platzner, “An Adaption Mechanism for the Error Threshold of XCSF,”10.1145/3377929.3398106__in GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico, 2020, pp. 1756–1764, doi:10.1145/3377929.3398106 .
LibreCat: /record/17063
DOI: 10.1145/3377929.3398106

M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “A Hybrid Synthesis Methodology for Approximate Circuits,” in Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, Beijing, China, 2020, pp. 421–426.
LibreCat: /record/16213
DOI: 10.1145/3386263.3406952

T. Hansmeier, P. Kaufmann, and M. Platzner, “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold,” in GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico, 2020, pp. 125–126.
LibreCat: /record/16363
DOI: 10.1145/3377929.3389968

A. Lösch and M. Platzner, “MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes,”10.1109/ipdpsw50202.2020.00012__2020, doi:10.1109/ipdpsw50202.2020.00012 .
LibreCat: /record/20838
DOI: 10.1109/ipdpsw50202.2020.00012

A. Lösch and M. Platzner, “MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes,”10.1109/IPDPSW50202.2020.00012__in 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020, pp. 6–16, doi:10.1109/IPDPSW50202.2020.00012 .
LibreCat: /record/35152
DOI: 10.1109/IPDPSW50202.2020.00012

L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth Workshop on Approximate Computing (AxC 2019). .
LibreCat: /record/16853

L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” in Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19, Tysons Corner, VA, USA, 2019.
LibreCat: /record/10577
DOI: 10.1145/3299874.3317998

N. Ho, P. Kaufmann, and M. Platzner, “Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor,” in World Congress on Nature and Biologically Inspired Computing (NaBIC), 2019.
LibreCat: /record/15422

Z. Guettatfi, M. Platzner, O. Kermia, and A. Khouas, “An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware,”10.1109/ipdpsw.2019.00027__2019, doi:10.1109/ipdpsw.2019.00027 .
LibreCat: /record/31067
DOI: 10.1109/ipdpsw.2019.00027

Q. A. Ahmed, T. Wiersema, and M. Platzner, “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan,”10.1007/978-3-030-17227-5_10__in Applied Reconfigurable Computing, Darmstadt, Germany, 2019, vol. 11444, pp. 127–136, doi:10.1007/978-3-030-17227-5_10 .
LibreCat: /record/9913
DOI: 10.1007/978-3-030-17227-5_10

A. Lösch, A. Wiens, and M. Platzner, “Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes,” in Proceedings of the International Conference on Architecture of Computing Systems (ARCS), 2018, vol. 10793, pp. 73–84.
LibreCat: /record/3362
DOI: 10.1007/978-3-319-77610-1_6

T. Hansmeier, M. Platzner, and D. Andrews, “An FPGA/HMC-Based Accelerator for Resolution Proof Checking,” in ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, Santorini, Greece, 2018, vol. 10824, pp. 153–165.
LibreCat: /record/3373
DOI: 10.1007/978-3-319-78890-6_13

L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Third Workshop on Approximate Computing (AxC 2018). .
LibreCat: /record/3586

L. M. Witschen, T. Wiersema, and M. Platzner, “Making the Case for Proof-carrying Approximate Circuits,” 4th Workshop On Approximate Computing (WAPCO 2018). 2018.
LibreCat: /record/1165

A. Lösch and M. Platzner, “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes,” in 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Milan, Italy, 2018.
LibreCat: /record/5547
DOI: 10.1109/asap.2018.8445098

M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “An MCTS-based Framework for Synthesis of Approximate Circuits,” in 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.
LibreCat: /record/10598
DOI: 10.1109/VLSI-SoC.2018.8645026

A. Lösch and M. Platzner, MinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements,” in Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2017.
LibreCat: /record/65
DOI: 10.1109/ASAP.2017.7995272

A. Boschmann, G. Thombansen, L. M. Witschen, A. Wiens, and M. Platzner, “A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller,” in Design, Automation and Test in Europe (DATE), 2017.
LibreCat: /record/10630
DOI: 10.23919/DATE.2017.7927137

N. Ho, I. I. Ashraf, P. Kaufmann, and M. Platzner, “Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor,” in Proc. Design, Automation and Test in Europe Conf. (DATE), 2017.
LibreCat: /record/10672
DOI: 10.23919/DATE.2017.7927096

N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor,” in 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.
LibreCat: /record/10676
DOI: 10.1109/FPT.2017.8280144