Q. A. Ahmed, T. Wiersema, and M. Platzner, “Post-configuration Activation of Hardware Trojans in FPGAs,”10.1007/s41635-024-00147-5__Journal of Hardware and Systems Security, 2024, doi:10.1007/s41635-024-00147-5 .
LibreCat: /record/52686
DOI: 10.1007/s41635-024-00147-5

F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, and M. Platzner, “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures,”10.1109/MM.2022.3202091__IEEE Micro, vol. 42, no. 6, pp. 125–133, 2022, doi:10.1109/MM.2022.3202091 .
LibreCat: /record/33990
DOI: 10.1109/MM.2022.3202091

M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware Co-Verification for Custom Instruction Set Processors,”10.1109/ACCESS.2021.3131213__IEEE Access, 2021, doi:10.1109/ACCESS.2021.3131213 .
LibreCat: /record/27841
DOI: 10.1109/ACCESS.2021.3131213

A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,”10.1109/tc.2021.3107196__IEEE Transactions on Computers, pp. 1–1, 2021, doi:10.1109/tc.2021.3107196 .
LibreCat: /record/30907
DOI: 10.1109/tc.2021.3107196

A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, and S. Dosen, “Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis,”10.1186/s12984-021-00822-6__Journal of NeuroEngineering and Rehabilitation, vol. 18, no. 1, Art. no. 25, 2021, doi:10.1186/s12984-021-00822-6 .
LibreCat: /record/30906
DOI: 10.1186/s12984-021-00822-6

C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,”10.1145/3494571__ACM Transactions on Reconfigurable Technology and Systems, pp. 1–20, 2021, doi:10.1145/3494571 .
LibreCat: /record/29150
DOI: 10.1145/3494571

L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, pp. 2084–2088, 2020.
LibreCat: /record/17358
DOI: 10.1109/TVLSI.2020.3008061

N. Ho, P. Kaufmann, and M. Platzner, “Evolution of Application-Specific Cache Mappings,” International Journal of Hybrid intelligent Systems, 2020.
LibreCat: /record/17369

J. Anwer, S. Meisner, and M. Platzner, “Dynamic Reliability Management for FPGA-Based Systems,” International Journal of Reconfigurable Computing, pp. 1–19, 2020.
LibreCat: /record/17092
DOI: 10.1155/2020/2808710

K. Bellman et al., “Self-aware Cyber-Physical Systems,” ACM Transactions on Cyber-Physical Systems, vol. Accepted for Publication, pp. 1–24, 2020.
LibreCat: /record/15836

M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,”10.1007/s00287-019-01187-w__Informatik Spektrum, 2019, doi:10.1007/s00287-019-01187-w .
LibreCat: /record/12871
DOI: 10.1007/s00287-019-01187-w

L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Microelectronics Reliability, vol. 99, pp. 277–290, 2019.
LibreCat: /record/3585
DOI: 10.1016/j.microrel.2019.04.003

T. Hansmeier, M. Platzner, M. J. H. Pantho, and D. Andrews, “An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology,” Journal of Signal Processing Systems, vol. 91, no. 11, pp. 1259–1272, 2019.
LibreCat: /record/12967
DOI: 10.1007/s11265-018-1435-y

A. Boschmann, A. Agne, G. Thombansen, L. M. Witschen, F. Kraus, and M. Platzner, “Zynq-based acceleration of robust high density myoelectric signal processing,” Journal of Parallel and Distributed Computing, vol. 123, pp. 77–89, 2019.
LibreCat: /record/11950
DOI: 10.1016/j.jpdc.2018.07.004

I. Ghribi, R. B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, and M. Platzner, “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints,” IEEE Access, pp. 14078–14092, 2018.
LibreCat: /record/12965
DOI: 10.1109/access.2018.2799852

T. Isenberg, M. Platzner, H. Wehrheim, and T. Wiersema, “Proof-Carrying Hardware via Inductive Invariants,” ACM Transactions on Design Automation of Electronic Systems, no. 4, pp. 61:1--61:23, 2017.
LibreCat: /record/68
DOI: 10.1145/3054743

C. Shen, P. Kaufmann, and M. Braun, “Fast Network Restoration by Partitioning of Parallel Black Start Zones,” The Journal of Engineering, p. 19pp, 2017.
LibreCat: /record/10740
DOI: 10.1049/joe.2017.0032

C. Shen, P. Kaufmann, and M. Braun, “Three-Stage Power System Restoration Methodology Considering Renewable Energies,” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 2017.
LibreCat: /record/10692

P. H.W. Leong et al., “The First 25 Years of the FPL Conference – Significant Papers,” ACM Transactions on Reconfigurable Technology and Systems, 2017.
LibreCat: /record/10600
DOI: 10.1145/2996468

R. F. DeMara, M. Platzner, and M. Ottavi, “Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial),” IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing, 2017.
LibreCat: /record/10601
DOI: 10.1109/TETC.2016.2641599

J. Anwer and M. Platzner, “Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus,” Microprocessors and Microsystems, pp. 160–172, 2017.
LibreCat: /record/10611
DOI: 10.1016/j.micpro.2017.06.002

C. Shen, P. Kaufmann, and M. Braun, “Three-Stage Power System Restoration Methodology Considering Renewable Energies,” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), vol. 94, pp. 287–299, 2017.
LibreCat: /record/9919
DOI: 10.1016/j.ijepes.2017.07.007

T. Wiersema, A. Bockhorn, and M. Platzner, “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip,” Computers &; Electrical Engineering, pp. 112--122, 2016.
LibreCat: /record/222
DOI: 10.1016/j.compeleceng.2016.04.005

C. Ma, P. Kaufmann, J.-C. Töbermann, and M. Braun, “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control,” Renewable Energy, vol. 87, no. (part 2), pp. 946–953, 2016.
LibreCat: /record/10705
DOI: 10.1016/j.renene.2015.07.083

H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, pp. 1–1, 2016.
LibreCat: /record/10769
DOI: 10.1109/TCAD.2016.2547908

T. Graf and M. Platzner, “Adaptive playouts for online learning of policies during Monte Carlo Tree Search,” Journal Theoretical Computer Science, vol. 644, pp. 53–62, 2016.
LibreCat: /record/10661
DOI: 10.1016/j.tcs.2016.06.029

C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,”10.1007/s00287-015-0911-z__Informatik Spektrum, no. 5, pp. 396–399, 2015, doi:10.1007/s00287-015-0911-z .
LibreCat: /record/1768
DOI: 10.1007/s00287-015-0911-z

T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,”10.1155/2015/859425__International Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015, doi:10.1155/2015/859425 .
LibreCat: /record/296
DOI: 10.1155/2015/859425

J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015.
LibreCat: /record/1772
DOI: 10.1109/MC.2015.205

H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires,” IEEE Transactions on Nanotechnology, vol. 14, no. 6, pp. 1117–1126, 2015.
LibreCat: /record/10770
DOI: 10.1109/TNANO.2015.2482359

H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,”10.1145/2641361.2641372__ACM SIGARCH Computer Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi:10.1145/2641361.2641372 .
LibreCat: /record/1779
DOI: 10.1145/2641361.2641372

A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,”10.1145/2617596__ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no. 13, 2014, doi:10.1145/2617596 .
LibreCat: /record/365
DOI: 10.1145/2617596

A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,”10.1016/j.micpro.2013.12.001__Microprocessors and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi:10.1016/j.micpro.2013.12.001 .
LibreCat: /record/363
DOI: 10.1016/j.micpro.2013.12.001

A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable Computing,”10.1109/MM.2013.110__IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi:10.1109/MM.2013.110 .
LibreCat: /record/328
DOI: 10.1109/MM.2013.110

L. Schaefers and M. Platzner, “A Novel Technique and its Application to Computer Go,” IEEE Transactions on Computational Intelligence and AI in Games, vol. 6, no. 3, pp. 361–374, 2014.
LibreCat: /record/10602
DOI: 10.1109/TCIAIG.2014.2346997

H. Giefers and M. Platzner, “An FPGA-based Reconfigurable Mesh Many-Core,” IEEE Transactions on Computers, vol. 63, no. 12, pp. 2919–2932, 2014.
LibreCat: /record/10603
DOI: 10.1109/TC.2013.174

S. Kasap and S. Redif, “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, pp. 522–536, 2013.
LibreCat: /record/1792
DOI: 10.1109/TVLSI.2013.2248069

P. Kaufmann, K. Glette, T. Gruber, M. Platzner, J. Torresen, and B. Sick, “Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers,” IEEE Transactions on Evolutionary Computation, vol. 17, no. 1, pp. 46–63, 2013.
LibreCat: /record/10684
DOI: 10.1109/TEVC.2012.2185845

M. Happe, E. Lübbers, and M. Platzner, “A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking,” International Journal of Real-time Image Processing, vol. 8, no. 1, pp. 95–110, 2013.
LibreCat: /record/10604
DOI: doi:10.1007/s11554-011-0212-y

M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,”10.1155/2012/418315__Int. Journal of Reconfigurable Computing (IJRC), 2012, doi:10.1155/2012/418315 .
LibreCat: /record/2177
DOI: 10.1155/2012/418315

T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,”10.1016/j.micpro.2011.04.002__Microprocessors and Microsystems, vol. 36, no. 2, pp. 110–126, 2012, doi:10.1016/j.micpro.2011.04.002 .
LibreCat: /record/2108
DOI: 10.1016/j.micpro.2011.04.002

K. Thielemans et al., “STIR: Software for Tomographic Image Reconstruction Release 2,” Physics in Medicine and Biology, vol. 57, no. 4, pp. 867–883, 2012.
LibreCat: /record/2172
DOI: 10.1088/0031-9155/57/4/867

S. Redif and S. Kasap, “Parallel algorithm for computation of second-order sequential best rotations,” Int. Journal of Electronics, vol. 100, no. 12, pp. 1646–1651, 2012.
LibreCat: /record/2173
DOI: 10.1080/00207217.2012.751343

S. Kasap and K. Benkrid, “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer,” Journal of Computers, vol. 7, no. 6, pp. 1312–1328, 2012.
LibreCat: /record/2174

P. Kaufmann, K. Glette, M. Platzner, and J. Torresen, “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture,” International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), vol. 3, no. 4, pp. 17–31, 2012.
LibreCat: /record/10685
DOI: 10.4018/jaras.2012100102

T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study,”10.1155/2011/760954__Int. Journal of Recon- figurable Computing (IJRC), 2011, doi:10.1155/2011/760954 .
LibreCat: /record/2201
DOI: 10.1155/2011/760954

U. Kebschull, M. Platzner, and J. Teich, “Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial),” IET Computers Digital Techniques, vol. 4, no. 3, pp. 157–158, 2010.
LibreCat: /record/10694
DOI: 10.1049/iet-cdt.2010.9044

S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification,” International Journal of Reconfigurable Computing, vol. 2010, 2010.
LibreCat: /record/10605
DOI: 10.1155/2010/180242

E. Lübbers and M. Platzner, “ReconOS: Multithreaded Programming for Reconfigurable Computers,” ACM Transactions on Embedded Computing Systems, vol. 9, no. 1, pp. 8:1-8:33, 2009.
LibreCat: /record/10703
DOI: 10.1145/1596532.1596540

K. Danne, R. Mühlenbernd, and M. Platzner, “Server-based execution of periodic tasks on dynamically reconfigurable hardware,” IET Computers Digital Techniques, vol. 1, no. 4, pp. 295–302, 2007.
LibreCat: /record/10646
DOI: 10.1049/iet-cdt:20060186

N. Bergmann, M. Platzner, and J. Teich, “Dynamically Reconfigurable Architectures (editorial),” EURASIP Journal on Embedded Systems, vol. 2007, pp. 1–2, 2007.
LibreCat: /record/10625
DOI: 10.1155/2007/28405

R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” Microprocessors and Microsystems, vol. 29, no. 2–3, pp. 63–73, 2005.
LibreCat: /record/2412
DOI: 10.1016/j.micpro.2004.06.004

C. Steiger, H. Walder, and M. Platzner, “Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks,” IEEE Transactions on Computers, vol. 53, no. 11, pp. 1393–1407, 2004.
LibreCat: /record/10742
DOI: 10.1109/tc.2004.99

C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” Journal of Supercomputing, vol. 26, no. 2, pp. 109–129, 2003.
LibreCat: /record/2420
DOI: 10.1023/a:1024443416592

C. Plessl et al., “The Case for Reconfigurable Hardware in Wearable Computing,” Personal and Ubiquitous Computing, vol. 7, no. 5, pp. 299–308, 2003.
LibreCat: /record/2419
DOI: 10.1007/s00779-003-0243-x

M. Eisenring and M. Platzner, “A Framework for Run-time Reconfigurable Systems,” The Journal of Supercomputing, vol. 21, no. 2, pp. 145–159, 2002.
LibreCat: /record/10651
DOI: 10.1023/a:1013627403946

O. Mencer, M. Platzner, M. Morf, and M. J. Flynn, “Object-oriented domain specific compilers for programming FPGAs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 1, pp. 205–210, 2001.
LibreCat: /record/10713
DOI: 10.1109/92.920835

M. Platzner, “Reconfigurable accelerators for combinatorial problems,” Computer, vol. 33, no. 4, pp. 58–60, 2000.
LibreCat: /record/6507
DOI: 10.1109/2.839322

M. Platzner, B. Rinner, and R. Weiss, “Toward embedded qualitative simulation: a specialized computer architecture for QSim,” IEEE Intelligent Systems, vol. 15, no. 2, pp. 62–68, 2000.
LibreCat: /record/10725
DOI: 10.1109/5254.850829

M. Eisenring and M. Platzner, “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems,” IEE Proceedings -- Computers &; Digital Techniques, vol. 147, pp. 159–165, 2000.
LibreCat: /record/10606
DOI: 10.1049/ip-cdt:20000496

M. Platzner, “Reconfigurable Computer Architectures,” e&;i Elektrotechnik und Informationstechnik, vol. 115, pp. 143–148, 1998.
LibreCat: /record/10607

M. Platzner and B. Rinner, “Design and Implementation of a Parallel Constraint Satisfaction Algorithm,” International Journal of Computers &; Their Applications, vol. 5, pp. 106–116, 1998.
LibreCat: /record/10608

M. Platzner, B. Rinner, and R. Weiss, “Parallel qualitative simulation,” Simulation Practice and Theory, vol. 5, no. 7–8, pp. 623–638, 1997.
LibreCat: /record/10724
DOI: 10.1016/s0928-4869(97)00008-6

M. Platzner, B. Rinner, and R. Weiss, “A Computer Architecture to Support Qualitative Simulation in Industrial Applications,” e &; i Elektrotechnik und Informationstechnik, vol. 114, pp. 13–18, 1997.
LibreCat: /record/10609

M. Platzner, B. Rinner, and R. Weiss, “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation,” J.UCS Journal of Universal Computer Science, vol. 12, pp. 811–820, 1995.
LibreCat: /record/10610

M. Platzner and C. Steger, “Erfahrungen mit einer Multi-Signalprozessorarchitektur (TM0),” Mikroelektronik, 1993.
LibreCat: /record/13466