Ahmed, Qazi Arbab, et al. “Post-Configuration Activation of Hardware Trojans in FPGAs.”10.1007/s41635-024-00147-5__Journal of Hardware and Systems Security, Springer Science and Business Media LLC, 2024, doi:10.1007/s41635-024-00147-5.

Jentzsch, Felix, et al. “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures.”10.1109/MM.2022.3202091__IEEE Micro, vol. 42, no. 6, IEEE, 2022, pp. 125–33, doi:10.1109/MM.2022.3202091.

Jakobs, Marie-Christine, et al. “Software/Hardware Co-Verification for Custom Instruction Set Processors.”10.1109/ACCESS.2021.3131213__IEEE Access, IEEE, 2021, doi:10.1109/ACCESS.2021.3131213.

Rodriguez, Alfonso, et al. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.”10.1109/tc.2021.3107196__IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1–1, doi:10.1109/tc.2021.3107196.

Boschmann, Alexander, et al. “Immersive Augmented Reality System for the Training of Pattern Classification Control with a Myoelectric Prosthesis.”10.1186/s12984-021-00822-6__Journal of NeuroEngineering and Rehabilitation, vol. 18, no. 1, 25, Springer Science and Business Media LLC, 2021, doi:10.1186/s12984-021-00822-6.

Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable Robotics Systems with ReconROS.”10.1145/3494571__ACM Transactions on Reconfigurable Technology and Systems, 2021, pp. 1–20, doi:10.1145/3494571.

Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.”10.1109/TVLSI.2020.3008061__IEEE Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, IEEE, 2020, pp. 2084–88, doi:10.1109/TVLSI.2020.3008061.

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Anwer, Jahanzeb, et al. “Dynamic Reliability Management for FPGA-Based Systems.”10.1155/2020/2808710__International Journal of Reconfigurable Computing, 2020, pp. 1–19, doi:10.1155/2020/2808710.

Bellman, K., et al. “Self-Aware Cyber-Physical Systems.” ACM Transactions on Cyber-Physical Systems, vol. Accepted for Publication, 2020, pp. 1–24.

Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.”10.1007/s00287-019-01187-w__Informatik Spektrum, 2019, doi:10.1007/s00287-019-01187-w.

Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.”10.1016/j.microrel.2019.04.003__Microelectronics Reliability, vol. 99, Elsevier, 2019, pp. 277–90, doi:10.1016/j.microrel.2019.04.003.

Hansmeier, Tim, et al. “An Accelerator for Resolution Proof Checking Based on FPGA and Hybrid Memory Cube Technology.”10.1007/s11265-018-1435-y__Journal of Signal Processing Systems, vol. 91, no. 11, 2019, pp. 1259–72, doi:10.1007/s11265-018-1435-y.

Boschmann, Alexander, et al. “Zynq-Based Acceleration of Robust High Density Myoelectric Signal Processing.”10.1016/j.jpdc.2018.07.004__Journal of Parallel and Distributed Computing, vol. 123, Elsevier, 2019, pp. 77–89, doi:10.1016/j.jpdc.2018.07.004.

Ghribi, Ines, et al. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints.”10.1109/access.2018.2799852__IEEE Access, 2018, pp. 14078–92, doi:10.1109/access.2018.2799852.

Isenberg, Tobias, et al. “Proof-Carrying Hardware via Inductive Invariants.”10.1145/3054743__ACM Transactions on Design Automation of Electronic Systems, no. 4, ACM, 2017, pp. 61:1--61:23, doi:10.1145/3054743.

Shen, Cong, et al. “Fast Network Restoration by Partitioning of Parallel Black Start Zones.”10.1049/joe.2017.0032__The Journal of Engineering, 2017, p. 19pp, doi:10.1049/joe.2017.0032.

Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 2017.

H.W. Leong, Philip, et al. “The First 25 Years of the FPL Conference – Significant Papers.”10.1145/2996468__ACM Transactions on Reconfigurable Technology and Systems, 2017, doi:10.1145/2996468.

F. DeMara, Ronald, et al. “Innovation in Reconfigurable Computing Fabrics: From Devices to Architectures (Guest Editorial).”10.1109/TETC.2016.2641599__IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing, 2017, doi:10.1109/TETC.2016.2641599.

Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant FPGA Structures Using Boolean Difference Calculus.”10.1016/j.micpro.2017.06.002__Microprocessors and Microsystems, Elsevier, 2017, pp. 160–72, doi:10.1016/j.micpro.2017.06.002.

Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.”10.1016/j.ijepes.2017.07.007__Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), vol. 94, 2017, pp. 287–99, doi:10.1016/j.ijepes.2017.07.007.

Wiersema, Tobias, et al. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.”10.1016/j.compeleceng.2016.04.005__Computers &; Electrical Engineering, Elsevier, 2016, pp. 112--122, doi:10.1016/j.compeleceng.2016.04.005.

Ma, Chenjie, et al. “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control.”10.1016/j.renene.2015.07.083__Renewable Energy, vol. 87, no. (part 2), Elsevier, 2016, pp. 946–53, doi:10.1016/j.renene.2015.07.083.

Ghasemzadeh Mohammadi, Hassan, et al. “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.”10.1109/TCAD.2016.2547908__IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, IEEE, 2016, pp. 1–1, doi:10.1109/TCAD.2016.2547908.

Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning of Policies during Monte Carlo Tree Search.”10.1016/j.tcs.2016.06.029__Journal Theoretical Computer Science, vol. 644, Elsevier, 2016, pp. 53–62, doi:10.1016/j.tcs.2016.06.029.

Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.”10.1007/s00287-015-0911-z__Informatik Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.

Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.”10.1155/2015/859425__International Journal of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.

Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.”10.1109/MC.2015.205__IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205.

Ghasemzadeh Mohammadi, Hassan, et al. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires.”10.1109/TNANO.2015.2482359__IEEE Transactions on Nanotechnology, vol. 14, no. 6, IEEE, 2015, pp. 1117–26, doi:10.1109/TNANO.2015.2482359.

Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.”10.1145/2641361.2641372__ACM SIGARCH Computer Architecture News, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:10.1145/2641361.2641372.

Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.”10.1145/2617596__ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596.

Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.”10.1016/j.micpro.2013.12.001__Microprocessors and Microsystems, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.

Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.”10.1109/MM.2013.110__IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.

Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application to Computer Go.”10.1109/TCIAIG.2014.2346997__IEEE Transactions on Computational Intelligence and AI in Games, vol. 6, no. 3, 2014, pp. 361–74, doi:10.1109/TCIAIG.2014.2346997.

Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh Many-Core.”10.1109/TC.2013.174__IEEE Transactions on Computers, vol. 63, no. 12, 2014, pp. 2919–32, doi:10.1109/TC.2013.174.

Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.”10.1109/TVLSI.2013.2248069__IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, IEEE, 2013, pp. 522–36, doi:10.1109/TVLSI.2013.2248069.

Kaufmann, Paul, et al. “Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers.”10.1109/TEVC.2012.2185845__IEEE Transactions on Evolutionary Computation, vol. 17, no. 1, 2013, pp. 46–63, doi:10.1109/TEVC.2012.2185845.

Happe, Markus, et al. “A Self-Adaptive Heterogeneous Multi-Core Architecture for Embedded Real-Time Video Object Tracking.”doi:10.1007/s11554-011-0212-y__International Journal of Real-Time Image Processing, vol. 8, no. 1, Springer, 2013, pp. 95–110, doi:doi:10.1007/s11554-011-0212-y.

Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.”10.1155/2012/418315__Int. Journal of Reconfigurable Computing (IJRC), Hindawi Publishing Corp., 2012, doi:10.1155/2012/418315.

Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.”10.1016/j.micpro.2011.04.002__Microprocessors and Microsystems, vol. 36, no. 2, 2012, pp. 110–26, doi:10.1016/j.micpro.2011.04.002.

Thielemans, Kris, et al. “STIR: Software for Tomographic Image Reconstruction Release 2.”10.1088/0031-9155/57/4/867__Physics in Medicine and Biology, vol. 57, no. 4, IOP Publishing, 2012, pp. 867–83, doi:10.1088/0031-9155/57/4/867.

Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.”10.1080/00207217.2012.751343__Int. Journal of Electronics, vol. 100, no. 12, Taylor &; Francis, 2012, pp. 1646–51, doi:10.1080/00207217.2012.751343.

Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers, vol. 7, no. 6, Academy Publishers, 2012, pp. 1312–28.

Kaufmann, Paul, et al. “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.”10.4018/jaras.2012100102__International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), vol. 3, no. 4, IGI Global, 2012, pp. 17–31, doi:10.4018/jaras.2012100102.

Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.”10.1155/2011/760954__Int. Journal of Recon- Figurable Computing (IJRC), Hindawi Publishing Corp., 2011, doi:10.1155/2011/760954.

Kebschull, Udo, et al. “Selected Papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (Editorial).”10.1049/iet-cdt.2010.9044__IET Computers Digital Techniques, vol. 4, no. 3, 2010, pp. 157–58, doi:10.1049/iet-cdt.2010.9044.

Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification.”10.1155/2010/180242__International Journal of Reconfigurable Computing, vol. 2010, Hindawi Publishing Corporation, 2010, doi:10.1155/2010/180242.

Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for Reconfigurable Computers.”10.1145/1596532.1596540__ACM Transactions on Embedded Computing Systems, vol. 9, no. 1, 2009, pp. 8:1-8:33, doi:10.1145/1596532.1596540.

Danne, Klaus, et al. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.”10.1049/iet-cdt:20060186__IET Computers Digital Techniques, vol. 1, no. 4, 2007, pp. 295–302, doi:10.1049/iet-cdt:20060186.

Bergmann, Neil, et al. “Dynamically Reconfigurable Architectures (Editorial).”10.1155/2007/28405__EURASIP Journal on Embedded Systems, vol. 2007, Springer Science+Business Media, 2007, pp. 1–2, doi:10.1155/2007/28405.

Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.”10.1016/j.micpro.2004.06.004__Microprocessors and Microsystems, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:10.1016/j.micpro.2004.06.004.

Steiger, Christoph, et al. “Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks.”10.1109/tc.2004.99__IEEE Transactions on Computers, vol. 53, no. 11, 2004, pp. 1393–407, doi:10.1109/tc.2004.99.

Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.”10.1023/a:1024443416592__Journal of Supercomputing, vol. 26, no. 2, Kluwer Academic Publishers, 2003, pp. 109–29, doi:10.1023/a:1024443416592.

Plessl, Christian, et al. “The Case for Reconfigurable Hardware in Wearable Computing.”10.1007/s00779-003-0243-x__Personal and Ubiquitous Computing, vol. 7, no. 5, Springer, 2003, pp. 299–308, doi:10.1007/s00779-003-0243-x.

Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable Systems.”10.1023/a:1013627403946__The Journal of Supercomputing, vol. 21, no. 2, Kluwer Academic Publishers, 2002, pp. 145–59, doi:10.1023/a:1013627403946.

Mencer, Oskar, et al. “Object-Oriented Domain Specific Compilers for Programming FPGAs.”10.1109/92.920835__IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 1, 2001, pp. 205–10, doi:10.1109/92.920835.

Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.”10.1109/2.839322__Computer, vol. 33, no. 4, Institute of Electrical and Electronics Engineers (IEEE), 2000, pp. 58–60, doi:10.1109/2.839322.

Platzner, Marco, et al. “Toward Embedded Qualitative Simulation: A Specialized Computer Architecture for QSim.”10.1109/5254.850829__IEEE Intelligent Systems, vol. 15, no. 2, Institute of Electrical \'26; Electronics Engineers (IEEE), 2000, pp. 62–68, doi:10.1109/5254.850829.

Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems.”10.1049/ip-cdt:20000496__IEE Proceedings -- Computers &; Digital Techniques, vol. 147, IET, 2000, pp. 159–65, doi:10.1049/ip-cdt:20000496.

Platzner, Marco. “Reconfigurable Computer Architectures.” E&;i Elektrotechnik Und Informationstechnik, vol. 115, Springer, 1998, pp. 143–48.

Platzner, Marco, and Bernhard Rinner. “Design and Implementation of a Parallel Constraint Satisfaction Algorithm.” International Journal of Computers &; Their Applications, vol. 5, ISCA, 1998, pp. 106–16.

Platzner, Marco, et al. “Parallel Qualitative Simulation.”10.1016/s0928-4869(97)00008-6__Simulation Practice and Theory, vol. 5, no. 7–8, Elsevier, 1997, pp. 623–38, doi:10.1016/s0928-4869(97)00008-6.

Platzner, Marco, et al. “A Computer Architecture to Support Qualitative Simulation in Industrial Applications.” E &; i Elektrotechnik Und Informationstechnik, vol. 114, Springer, 1997, pp. 13–18.

Platzner, Marco, et al. “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation.” J.UCS Journal of Universal Computer Science, vol. 12, Springer, 1995, pp. 811–20.

Platzner, Marco, and Christian Steger. “Erfahrungen mit einer Multi-Signalprozessorarchitektur (TM0).” Mikroelektronik, 1993.