Noctua 2 Supercomputer
C. Bauer, T. Kenter, M. Lass, L. Mazur, M. Meyer, H. Nitsche, H. Riebler, R. Schade, M. Schwarz, N. Winnwa, A. Wiens, X. Wu, C. Plessl, J. Simon, Journal of Large-Scale Research Facilities 9 (2024).
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DOI: 10.17815/jlsrf-8-187 

Transparent Control Flow Transfer between CPU and Accelerators for HPC
D. Granhão, J.C. Canas Ferreira, Electronics (2021).
LibreCat: /record/21208
DOI: 10.3390/electronics10040406

OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors
D. Castells-Rufas, S. Marco-Sola, Q. Aguado-Puig, A. Espinosa-Morales, J.C. Moure, L. Alvarez, M. Moreto, in: 2021 31st International Conference on Field-Programmable Logic and Applications (FPL), IEEE, 2021.
LibreCat: /record/35131
DOI: 10.1109/fpl53798.2021.00036

Exploration of FPGA-Based Hardware Designs for QR Decomposition for Solving Stiff ODE Numerical Methods Using the HARP Hybrid Architecture
C. Alberto Oliveira de Souza Junior, J. Bispo, J.M.P. Cardoso, P.C. Diniz, E. Marques, Electronics (2020).
LibreCat: /record/17359
DOI: 10.3390/electronics9050843

Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL
H. Wang, P. Thiagaraj, O. Sinnen, Journal of Astronomical Instrumentation (2019).
LibreCat: /record/16420
DOI: 10.1142/s2251171719500089

Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL
T. Faict, E.H. D’Hollander, B. Goossens, Algorithms (2019).
LibreCat: /record/16422
DOI: 10.3390/a12080149

Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform
A. Rodríguez, A. Navarro, R. Asenjo, F. Corbera, R. Gran, D. Suárez, J. Nunez-Yanez, The Journal of Supercomputing (2019).
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Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package
M.A. Souza, L.A. Maciel, P.H. Penna, H.C. Freitas, in: 2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2019.
LibreCat: /record/16411
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Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators
L. Sommer, J. Oppermann, A. Molina, C. Binnig, K. Kersting, A. Koch, in: 2018 IEEE 36th International Conference on Computer Design (ICCD), 2019.
LibreCat: /record/16413
DOI: 10.1109/iccd.2018.00060

Constructing Concurrent Data Structures on FPGA with Channels
H. Yan, Z. Li, L. Liu, S. Yin, S. Wei, in: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019.
LibreCat: /record/16417
DOI: 10.1145/3289602.3293921

FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory
Z. Li, L. Liu, Y. Deng, J. Wang, Z. Liu, S. Yin, S. Wei, in: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019.
LibreCat: /record/16427
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Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution
Z. Li, L. Liu, Y. Deng, S. Yin, S. Wei, IEEE Computer Architecture Letters (2018) 147–150.
LibreCat: /record/16416
DOI: 10.1109/lca.2018.2828402

Automatic Offloading of Cluster Accelerators
C. Ceissler, R. Nepomuceno, M. Pereira, G. Araujo, in: 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2018.
LibreCat: /record/16421
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A Case Study in Using OpenCL on FPGAs: Creating an Open-Source Accelerator of the AutoDock Molecular Docking Software
L. Solis-Vasquez, A. Koch, in: FSP Workshop 2018; Fifth International Workshop on FPGAs for Software Programmers, 2018, pp. 1–10.
LibreCat: /record/16425