Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., &; Wunderlich, H.-J. (n.d.). Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. European Test Symposium, The Hague, Netherlands, May 20-24, 2024, 6.
LibreCat: /record/52744

Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., &; Wunderlich, H.-J. (n.d.). Vmin Testing under Variations: Defect vs. Fault Coverage. IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, 6.
LibreCat: /record/52742

Hellebrand, S., Sadeghi-Kohan, S., &; Wunderlich, H.-J. (n.d.). Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.
LibreCat: /record/52743

Wunderlich, H.-J., Jafarzadeh, H., &; Hellebrand, S. (n.d.). Robust Test of Small Delay Faults under  PVT-Variations. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.
LibreCat: /record/52745

Stiballe, A., Reimer, J. D., Sadeghi-Kohan, S., &; Hellebrand, S. (2024). Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024.
LibreCat: /record/50284

Ustimova, M., Sadeghi-Kohan, S., &; Hellebrand, S. (2024). Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024.
LibreCat: /record/51799

Ghazal, A., Sadeghi-Kohan, S., Reimer, J. D., &; Hellebrand, S. (2023). On Cryptography Effects on Interconnect Reliability. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023.
LibreCat: /record/35204

Badran, A., Sadeghi-Kohan, S., Reimer, J. D., &; Hellebrand, S. (2023). Approximate Computing: Balancing Performance, Power, Reliability, and Safety. 28th IEEE European Test Symposium (ETS’23), May 2023.
LibreCat: /record/41875

Sadeghi-Kohan, S., Hellebrand, S., &; Wunderlich, H.-J. (2023). Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W).https://doi.org/10.1109/dsn-w58399.2023.00056 
LibreCat: /record/46739
DOI: 10.1109/dsn-w58399.2023.00056

Sadeghi-Kohan, S., Reimer, J. D., Hellebrand, S., &; Wunderlich, H.-J. (2023). Optimizing the Streaming of Sensor Data with Approximate Communication. IEEE Asian Test Symposium (ATS’23), October 2023. IEEE Asian Test Symposium (ATS’23).
LibreCat: /record/46738

Sadeghi-Kohan, S., Hellebrand, S., &; Wunderlich, H.-J. (2023). Workload-Aware Periodic Interconnect BIST. IEEE Design &;Test, 1–1.https://doi.org/10.1109/mdat.2023.3298849 
LibreCat: /record/46264
DOI: 10.1109/mdat.2023.3298849

Jafarzadeh, H., Klemme, F., Reimer, J. D., Najafi Haghi, Z. P.,  Amrouch, H., Hellebrand, S., &;  Wunderlich, H.-J. (2023). Robust Pattern Generation for Small Delay Faults under Process Variations. IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE International Test Conference (ITC’23), Anaheim, USA.
LibreCat: /record/45830

Sadeghi-Kohan, S., Hellebrand, S., &; Wunderlich, H.-J. (2022). Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing.https://doi.org/10.1007/s10836-021-05979-5 
LibreCat: /record/29351
DOI: 10.1007/s10836-021-05979-5

Sadeghi-Kohan, S., Hellebrand, S., &; Wunderlich, H.-J. (2022). EM-Aware Interconnect BIST. European Workshop on Silicon Lifecycle Management, March 18, 2022.
LibreCat: /record/29890

Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., &; Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020.
LibreCat: /record/19422

Sadeghi-Kohan, S., &; Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020.
LibreCat: /record/15419

Sadeghi-Kohan, S., &; Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 38th IEEE VLSI Test Symposium (VTS).https://doi.org/10.1109/vts48691.2020.9107591 
LibreCat: /record/29200
DOI: 10.1109/vts48691.2020.9107591

Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich, H.-J., &; Weng, X. (2020). Logic Fault Diagnosis of Hidden Delay Defects. IEEE International Test Conference (ITC’20), November 2020.
LibreCat: /record/19421

Maaz, M. U., Sprenger, A., &; Hellebrand, S. (2019). A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19).
LibreCat: /record/8112

Sprenger, A., &; Hellebrand, S. (2019). Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers, 28(1), 1–23.https://doi.org/10.1142/s0218126619400012 
LibreCat: /record/8667
DOI: 10.1142/s0218126619400012

Kampmann, M., A. Kochte, M., Liu, C., Schneider, E., Hellebrand, S., &; Wunderlich, H.-J. (2019). Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(10), 1956–1968.
LibreCat: /record/13048

Maaz, M. U., Sprenger, A., &; Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. 50th IEEE International Test Conference (ITC), 1–8.
LibreCat: /record/12918

Sprenger, A., &; Hellebrand, S. (2018). Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18).
LibreCat: /record/4576

Hellebrand, S., Henkel, J., Raghunathan, A., &; Wunderlich, H.-J. (2018). Guest Editors’ Introduction - Special Issue on Approximate Computing. IEEE Embedded Systems Letters, 10(1), 1–1.https://doi.org/10.1109/les.2018.2789942 
LibreCat: /record/12974
DOI: 10.1109/les.2018.2789942

Kampmann, M., &; Hellebrand, S. (2018). Design For Small Delay Test - A Simulation Study. Microelectronics Reliability, 80, 124–133.
LibreCat: /record/13057

Sprenger, A., &; Hellebrand, S. (2018). Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &; Systems (DDECS).https://doi.org/10.1109/ddecs.2018.00020 
LibreCat: /record/4575
DOI: 10.1109/ddecs.2018.00020

Liu, C., Schneider, E., Kampmann, M., Hellebrand, S., &; Wunderlich, H.-J. (2018). Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. 27th IEEE Asian Test Symposium (ATS’18).https://doi.org/10.1109/ats.2018.00028 
LibreCat: /record/10575
DOI: 10.1109/ats.2018.00028

Deshmukh, J., Kunz, W., Wunderlich, H.-J., &; Hellebrand, S. (2017). Special Session on Early Life Failures. In 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE.https://doi.org/10.1109/vts.2017.7928933 
LibreCat: /record/12973
DOI: 10.1109/vts.2017.7928933

Kampmann, M., &; Hellebrand, S. (2017). X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz.
LibreCat: /record/13078

Kampmann, M., &; Hellebrand, S. (2017). Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. 20th IEEE International Symposium on Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’17).https://doi.org/10.1109/ddecs.2017.7934564 
LibreCat: /record/10576
DOI: 10.1109/ddecs.2017.7934564

Kampmann, M., &; Hellebrand, S. (2016). X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. In 25th IEEE Asian Test Symposium (ATS’16) (pp. 1–6). Hiroshima, Japan: IEEE.https://doi.org/10.1109/ats.2016.20 
LibreCat: /record/12975
DOI: 10.1109/ats.2016.20

Kampmann, M., A. Kochte, M., Schneider, E., Indlekofer, T., Hellebrand, S., &; Wunderlich, H.-J. (2015). Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In 24th IEEE Asian Test Symposium (ATS’15) (pp. 109–114). Mumbai, India: IEEE.https://doi.org/10.1109/ats.2015.26 
LibreCat: /record/12976
DOI: 10.1109/ats.2015.26

Huang, Z., Liang, H., &; Hellebrand, S. (2015). A High Performance SEU Tolerant Latch. Journal of Electronic Testing - Theory and Applications (JETTA), 31(4), 349–359.
LibreCat: /record/13056

Hellebrand, S., Indlekofer, T., Kampmann, M., Kochte, M., Liu, C., &; Wunderlich, H.-J. (2015). Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany.
LibreCat: /record/13077

Hellebrand, S., Indlekofer, T., Kampmann, M., A. Kochte, M., Liu, C., &; Wunderlich, H.-J. (2014). FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In IEEE International Test Conference (ITC’14). Seattle, Washington, USA: IEEE.https://doi.org/10.1109/test.2014.7035360 
LibreCat: /record/12977
DOI: 10.1109/test.2014.7035360

Hellebrand, S., &; Wunderlich, H.-J. (2014). SAT-Based ATPG beyond Stuck-at Fault Testing. DeGruyter Journal on Information Technology (It), 56(4), 165–172.
LibreCat: /record/13054

Rodriguez Gomez, L., Cook, A., Indlekofer, T., Hellebrand, S., &; Wunderlich, H.-J. (2014). Adaptive Bayesian Diagnosis of Intermittent Faults. Journal of Electronic Testing - Theory and Applications (JETTA), 30(5), 527–540.
LibreCat: /record/13055

Hellebrand, S. (2013). Analyzing and Quantifying Fault Tolerance Properties. In 14th IEEE Latin American Test Workshop - (LATW’13). Cordoba, Argentina: IEEE.https://doi.org/10.1109/latw.2013.6562662 
LibreCat: /record/12979
DOI: 10.1109/latw.2013.6562662

Cook, A., Rodriguez Gomez, L., Hellebrand, S., Indlekofer, T., &; Wunderlich, H.-J. (2013). Adaptive Test and Diagnosis of Intermittent Faults. 14th Latin American Test Workshop, Cordoba, Argentina.
LibreCat: /record/13075

Cook, A., Hellebrand, S., E. Imhof, M., Mumtaz, A., &; Wunderlich, H.-J. (2012). Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. In 13th IEEE Latin American Test Workshop (LATW’12) (pp. 1–4). Quito, Ecuador: IEEE.https://doi.org/10.1109/latw.2012.6261229 
LibreCat: /record/12980
DOI: 10.1109/latw.2012.6261229

Cook, A., Hellebrand, S., &; Wunderlich, H.-J. (2012). Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. In 17th IEEE European Test Symposium (ETS’12) (pp. 1–6). Annecy, France: IEEE.https://doi.org/10.1109/ets.2012.6233025 
LibreCat: /record/12981
DOI: 10.1109/ets.2012.6233025

Cook, A., Hellebrand, S., &; Wunderlich, H.-J. (2012). Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern. 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany.
LibreCat: /record/13074

Cook, A., Hellebrand, S., Indlekofer, T., &; Wunderlich, H.-J. (2011). Diagnostic Test of Robust Circuits. In 20th IEEE Asian Test Symposium (ATS’11) (pp. 285–290). New Delhi, India: IEEE.https://doi.org/10.1109/ats.2011.55 
LibreCat: /record/12982
DOI: 10.1109/ats.2011.55

Polian, I., Becker, B., Hellebrand, S., Wunderlich, H.-J., &; Maxwell, P. (2011). Towards Variation-Aware Test Methods. In 16th IEEE European Test Symposium Trondheim (ETS’11). Trondheim, Norway: IEEE.https://doi.org/10.1109/ets.2011.51 
LibreCat: /record/12984
DOI: 10.1109/ets.2011.51

Cook, A., Hellebrand, S., Indlekofer, T., &; Wunderlich, H.-J. (2011). Robuster Selbsttest mit Diagnose. In 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit und Entwurf” (pp. 48–53). Hamburg, Germany.
LibreCat: /record/13053

Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2011). Variation-Aware Fault Modeling. SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer, 54(4), 1813–1826.
LibreCat: /record/13052

Fröse, V., Ibers, R., &; Hellebrand, S. (2010). Testdatenkompression mit Hilfe der Netzwerkinfrastruktur. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany.
LibreCat: /record/10670

Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10). Chicago, IL, USA: IEEE.https://doi.org/10.1109/dsnw.2010.5542612 
LibreCat: /record/12987
DOI: 10.1109/dsnw.2010.5542612

Hunger, M., &; Hellebrand, S. (2010). Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf” (pp. 81–88). Wildbad Kreuth, Germany.
LibreCat: /record/13051

Hellebrand, S. (2010). Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180.
LibreCat: /record/13073