Analysis and Design of a Charge Sampler With 70-GHz 1-dB Bandwidth in 130-nm SiGe BiCMOS
L. Wu, J.C. Scheytt, IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2021) 3668–3681.
LibreCat: /record/29210
DOI: 10.1109/tcsi.2021.3094428

Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie für Analog-Digital-Wandler mit zeitversetzter Abtastung
L. Wu, Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie Für Analog-Digital-Wandler Mit Zeitversetzter Abtastung, 2021.
LibreCat: /record/52664

Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology
L. Wu, M. Weizel, C. Scheytt, in: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, Sevilla, Spain, 2020.
LibreCat: /record/24021
DOI: 10.1109/ISCAS45731.2020.9180947

70 GHz Large-signal Bandwidth Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology
L. Wu, M. Weizel, C. Scheytt, in: Asia-Pacific Microwave Conference (APMC), 2019.
LibreCat: /record/24049
DOI: 10.1109/APMC46564.2019.9038239

A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology
L. Wu, M. Weizel, C. Scheytt, in: 26th IEEE International Conference on Electronics Circuits and Systems (ICECS), Genova, Italy, 2019.
LibreCat: /record/24052
DOI: 10.1109/ICECS46596.2019.8965046

Analog fault simulation automation at schematic level with random sampling techniques
L. Wu, M.K. Hussain, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2018 13th International Conference on Design &; Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, Italy/Taormina, 2018.
LibreCat: /record/24196
DOI: 10.1109/DTIS.2018.8368549

Integrier und HalteSchaltung 
C. Scheytt, L. Wu, (2018).
LibreCat: /record/24198

SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study
L. Wu, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), Lausanne, Switzerland, 2017, p. 68.
LibreCat: /record/24223

Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study
S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, C. Novello, in: Analog 2016 - VDE, 2016.
LibreCat: /record/24263

On the Correlation of HW Faults and SW Errors
W. Müller, L. Wu, C. Scheytt, M. Becker, S. Schoenberg, in: D. Mueller-Gritschneder, W. Müller, S. Mitra (Eds.), Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), Amsterdam, Netherland, 2015.
LibreCat: /record/24289