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T. Kenter, A. Shambhu, S. Faghih-Naini, and V. Aizinger, “Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA,”10.1145/3468267.3470617__2021, doi:10.1145/3468267.3470617 .

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H. Mirhosseini, R. Kormath Madam Raghupathy, S. K. Sahoo, H. Wiebeler, M. Chugh, and T. D. Kühne, “In silico investigation of Cu(In,Ga)Se<sub>2</sub>-based solar cells,”10.1039/d0cp04712k__Physical Chemistry Chemical Physics, vol. 22, no. 46, pp. 26682–26701, 2020, doi:10.1039/d0cp04712k .

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M. Lass, R. Schade, T. Kühne, and C. Plessl, “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CK,”10.1109/SC41405.2020.00084__in Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Atlanta, GA, US, 2020, pp. 1127–1140, doi:10.1109/SC41405.2020.00084 .

M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite,”10.1109/h2rc51942.2020.00007__2020, doi:10.1109/h2rc51942.2020.00007 .

V. Rengaraj, M. Lass, C. Plessl, and T. Kühne, “Accurate Sampling with Noisy Forces from Approximate Computing,”10.3390/computation8020039__Computation, vol. 8, no. 2, Art. no. 39, 2020, doi:10.3390/computation8020039 .

H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL,” ACM Trans. Archit. Code Optim. (TACO), vol. 16, no. 2, pp. 14:1–14:26, 2019.

P. Gorlani, T. Kenter, and C. Plessl, “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2019.

H. Riebler, Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs. 2019.

D. Richters, M. Lass, A. Walther, C. Plessl, and T. Kühne, “A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices,”10.4208/cicp.OA-2018-0053__Communications in Computational Physics, vol. 25, no. 2, pp. 564–585, 2019, doi:10.4208/cicp.OA-2018-0053 .

M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,”10.1007/s00287-019-01187-w__Informatik Spektrum, 2019, doi:10.1007/s00287-019-01187-w .

M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots,” Embedded Systems Letters, vol. 10, no. 2, pp. 33–36, 2018.

A. Keller, “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems,” in Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Orlando, FL, USA, 2018, vol. 10773, pp. 132–151.

T. Filmwala, Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform. Universität Paderborn, 2018.

O. Gadewar, Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn, 2018.

J. C. Mertens, A. Boschmann, M. Schmidt, and C. Plessl, “Sprint diagnostic with GPS and inertial sensor fusion,” Sports Engineering, vol. 21, no. 4, pp. 441–451, 2018.

A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn, 2018.

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T. Kenter et al., “OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes,”10.1109/FCCM.2018.00037__presented at the Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2018, doi:10.1109/FCCM.2018.00037 .

M. Lass, S. Mohr, H. Wiebeler, T. Kühne, and C. Plessl, “A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices,”10.1145/3218176.3218231__presented at the Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland, 2018, doi:10.1145/3218176.3218231 .

H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices,”10.1145/3178487.3178534__2018, doi:10.1145/3178487.3178534 .

H. Riebler, M. Lass, R. Mittendorf, T. Löcke, and C. Plessl, “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs,”10.1145/3053687__ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, p. 24:1-24:23, 2017, doi:10.1145/3053687 .

T. Kenter, J. Förstner, and C. Plessl, “Flexible FPGA design for FDTD using OpenCL,”10.23919/FPL.2017.8056844__2017, doi:10.23919/FPL.2017.8056844 .

J. Schumacher, C. Plessl, and W. Vandelli, “High-Throughput and Low-Latency Network Communication with NetIO,”10.1088/1742-6596/898/8/082003__Journal of Physics: Conference Series, vol. 898, Art. no. 082003, 2017, doi:10.1088/1742-6596/898/8/082003 .

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C. Tölke, Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung. Universität Paderborn, 2016.

G. Wüllrich, Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment. Universität Paderborn, 2016.

T. Kenter, Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn, 2016.

A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in FPGAs for Software Programmers, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244.

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T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016.

M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific Codes,” 2016.

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A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in Self-aware Computing Systems, Cham: Springer International Publishing, 2016, pp. 145–165.

G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,”10.1016/j.compeleceng.2016.04.021__Computers and Electrical Engineering, vol. 55, pp. 91–111, 2016, doi:10.1016/j.compeleceng.2016.04.021 .

A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation &; Test in Europe Conference &; Exhibition (DATE), 2016, pp. 912–917.

T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016.

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M. Lass, Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing. Paderborn: Paderborn University, 2015.

L. Funke, An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures. Universität Paderborn, 2015.

T. Löcke, Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn, 2015.

F. Wallaschek, Accelerating Programmable Logic Controllers with the use of FPGAs. Universität Paderborn, 2015.

T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.

T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,”10.1155/2015/859425__International Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015, doi:10.1155/2015/859425 .

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M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,”10.7873/DATE.2015.1124__in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi:10.7873/DATE.2015.1124 .

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T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25.

M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in Logiken strukturbildender Prozesse: Automatismen, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144.

T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,”10.1007/978-3-319-05960-0_13__in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi:10.1007/978-3-319-05960-0_13 .

A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,”10.1016/j.micpro.2013.12.001__Microprocessors and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi:10.1016/j.micpro.2013.12.001 .

H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,”10.1109/FCCM.2014.67__in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi:10.1109/FCCM.2014.67 .

A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,”10.1145/2617596__ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no. 13, 2014, doi:10.1145/2617596 .

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G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,”10.1109/ReConFig.2014.7032509__in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509 .

T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,”10.1109/ReConFig.2014.7032535__in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535 .

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H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,”10.1145/2641361.2641372__ACM SIGARCH Computer Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi:10.1145/2641361.2641372 .

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S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications Conf. (SUI), 2013.

P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, and L. Nagel, “Distributing Storage in Cloud Environments,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013.

O. Niehörster, Autonomous Resource Management in Dynamic Data Centers. Aachen, Germany: Shaker, 2013.

D. Meister, Advanced Data Deduplication Techniques and Their Application. Johannes Gutenberg-Universität Mainz, 2013.

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D. Meister, A. Brinkmann, and T. Süß, “File Recipe Compression in Data Deduplication Systems,” in Proc. USENIX Conference on File and Storage Technologies (FAST), 2013, pp. 175–182.

H. Riebler, Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn, 2013.

H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,”10.1109/FPT.2013.6718394__in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi:10.1109/FPT.2013.6718394 .

M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,”10.1109/ISORC.2013.6913232__2013, doi:10.1109/ISORC.2013.6913232 .

T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,”10.1109/IPDPSW.2013.136__in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136 .

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S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2012, pp. 135–140.

J. Kaiser, D. Meister, T. Hartung, and A. Brinkmann, “ESB: Ext2 Split Block Device,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 2012, pp. 181–188.

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M. Wistuba, L. Schaefers, and M. Platzner, “Comparison of Bayesian Move Prediction Systems for Computer Go,” in Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 2012, pp. 91–99.