Maaz, M. U., Sprenger, A., &; Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. 50th IEEE International Test Conference (ITC), 1–8.

Sprenger, A., &; Hellebrand, S. (2018). Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18).

Hellebrand, S., Henkel, J., Raghunathan, A., &; Wunderlich, H.-J. (2018). Guest Editors’ Introduction - Special Issue on Approximate Computing. IEEE Embedded Systems Letters, 10(1), 1–1.https://doi.org/10.1109/les.2018.2789942 

Kampmann, M., &; Hellebrand, S. (2018). Design For Small Delay Test - A Simulation Study. Microelectronics Reliability, 80, 124–133.

Kampmann, M., &; Hellebrand, S. (2018). Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China.

Rezaeizadeh Rookerd, R., Sadeghi-Kohan, S., &; Navabi, Z. (2018). Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. Proceedings of the 2018 on Great Lakes Symposium on VLSI.https://doi.org/10.1145/3194554.3194599 

Sprenger, A., &; Hellebrand, S. (2018). Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &; Systems (DDECS).https://doi.org/10.1109/ddecs.2018.00020 

Liu, C., Schneider, E., Kampmann, M., Hellebrand, S., &; Wunderlich, H.-J. (2018). Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. 27th IEEE Asian Test Symposium (ATS’18).https://doi.org/10.1109/ats.2018.00028 

Sadeghi-Kohan, S., Vafaei, A., &; Navabi, Z. (2018). Near-Optimal Node Selection Procedure for Aging Monitor Placement. 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).https://doi.org/10.1109/iolts.2018.8474120 

Deshmukh, J., Kunz, W., Wunderlich, H.-J., &; Hellebrand, S. (2017). Special Session on Early Life Failures. In 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE.https://doi.org/10.1109/vts.2017.7928933