Becker, B., Polian, I., Hellebrand, S., Straube, B., &; Wunderlich, H.-J. (2006). DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme. It - Information Technology, 48(5), 305–311.

Oehler, P., &; Hellebrand, S. (2005). A Low Power Design for Embedded DRAMs with Online Consistency Checking. Kleinheubachertagung 2005, Miltenberg, Germany.

Ali, M., Welzl, M., &; Hellebrand, S. (2005). Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria.

Oehler, P., &; Hellebrand, S. (2005). Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria.

Ali, M., Welzl, M., Zwicknagl, M., &; Hellebrand, S. (2005). Considerations for Fault-Tolerant Networks on Chips. IEEE International Conference on Microelectronics (ICM’05).https://doi.org/10.1109/icm.2005.1590063 

Oehler, P., &; Hellebrand, S. (2005). Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. 10th IEEE European Test Symposium (ETS’05), 148–153.https://doi.org/10.1109/ets.2005.28 

Ali, M., Welzl, M., &; Hellebrand, S. (2005). A Dynamic Routing Mechanism for Network on Chip. 23rd IEEE NORCHIP Conference, 70–73.https://doi.org/10.1109/norchp.2005.1596991 

Liu Jing, M., Ruehrup, S., Schindelhauer, C., Volbert, K., Dierkes, M., Bellgardt, A.,  Hilleringmann, U. (2004). Sensor Networks with More Features Using Less Hardware. In GOR/NGB Conference Tilburg 2004. Tilburg, Netherlands.

Breu, R., Fahringer, T., Fensel, D., Hellebrand, S., Middeldorp, A., &; Scherzer, O. (2004). Im Westen viel Neues - Informatik an der Universität Innsbruck. OCG Journal, pp. 28-29.

Hellebrand, S., Wuertenberger, A., &; S. Tautermann, C. (2004). Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France.