Wuertenberger A, S. Tautermann C, Hellebrand S. Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. In: IEEE International Test Conference (ITC’04). IEEE; 2004:926-935. doi:10.1109/test.2004.1387357
LibreCat: /record/13001
DOI: 10.1109/test.2004.1387357

Breu R, Hellebrand S, Welzl M. Experiences from Teaching Software Development in a Java Environment. Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia; 2003.
LibreCat: /record/13098

Wuertenberger A, S. Tautermann C, Hellebrand S. A Hybrid Coding Strategy for Optimized Test Data Compression. In: IEEE International Test Conference (ITC’03). IEEE; 2003:451-459. doi:10.1109/test.2003.1270870
LibreCat: /record/13002
DOI: 10.1109/test.2003.1270870

Hellebrand S, Wuertenberger A. Alternating Run-Length Coding: A Technique for Improved Test Data Compression. IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA; 2002.
LibreCat: /record/13097

Hellebrand S, Wunderlich H-J, A. Ivaniuk A, V. Klimets Y, N. Yarmolik V. Efficient Online and Offline Testing of Embedded DRAMs. IEEE Transactions on Computers. 2002;51(7):801-809. doi:10.1109/tc.2002.1017700
LibreCat: /record/13003
DOI: 10.1109/tc.2002.1017700

Hellebrand S, Liang H-G, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Journal of Electronic Testing - Theory and Applications (JETTA). 2002;18(2):157-168.
LibreCat: /record/13069

Liang H, Hellebrand S, Wunderlich H-J. A Mixed-Mode BIST Scheme Based on Folding Compression. Journal on Computer Science and Technology. 2002;17(2):203-212.
LibreCat: /record/13070

Liang H-G, Hellebrand S, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE European Test Workshop, Stockholm, Sweden; 2001.
LibreCat: /record/13096

Liang H-G, Hellebrand S, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. In: IEEE International Test Conference (ITC’01). IEEE; 2001:894-902. doi:10.1109/test.2001.966712
LibreCat: /record/13004
DOI: 10.1109/test.2001.966712

Liang H-G, Hellebrand S, Wunderlich H-J. Deterministic BIST Scheme Based on Reseeding of Folding Counters. Journal of Computer Research and Development, (Jisuanji Yanjiu yu Fazhan). 2001;38(8):931.
LibreCat: /record/13047

Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Journal of Electronic Testing - Theory and Applications (JETTA). 2001;17(3/4):341-349.
LibreCat: /record/13068

Hellebrand S, Wunderlich H-J. Hardwarepraktikum Im Diplomstudiengang Informatik. Handbuch Lehre, Berlin, Raabe Verlag; 2000.
LibreCat: /record/13094

Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE European Test Workshop, Cascais, Portugal; 2000.
LibreCat: /record/13095

Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. In: IEEE International Test Conference (ITC’00). IEEE; 2000:778-784. doi:10.1109/test.2000.894274
LibreCat: /record/13005
DOI: 10.1109/test.2000.894274

Hellebrand S. Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren. Verlag Dr. Kovac, Hamburg: Verlag Dr. Kovac, Hamburg; 1999.
LibreCat: /record/13065

Hellebrand S, Wunderlich H-J, N. Yarmolik V. Exploiting Symmetries to Speed Up Transparent BIST. 11th GI/ITG/GMM/IEEE Workshop; 1999.
LibreCat: /record/13093

Hellebrand S, Wunderlich H-J, A. Ivaniuk A, V. Klimets Y, N. Yarmolik V. Error Detecting Refreshment for Embedded DRAMs. In: 17th IEEE VLSI Test Symposium (VTS’99). IEEE; 1999:384-390. doi:10.1109/vtest.1999.766693
LibreCat: /record/13006
DOI: 10.1109/vtest.1999.766693

N. Yarmolik V, V. Bykov I, Hellebrand S, Wunderlich H-J. Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. In: Third European Dependable Computing Conference (EDCC-3). ; 1999.
LibreCat: /record/13066

Hellebrand S, Wunderlich H-J, N. Yarmolik V. Symmetric Transparent BIST for RAMs. In: Design Automation and Test in Europe (DATE’99). ; 1999:702-707.
LibreCat: /record/13067

Hellebrand S, Wunderlich H-J. Test Und Synthese Schneller Eingebetteter Systeme. Universität Stuttgart; 1998.
LibreCat: /record/13029

N. Yarmolik V, Hellebrand S, Wunderlich H-J. Efficient Consistency Checking for Embedded Memories. 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA; 1998.
LibreCat: /record/13091

N. Yarmolik V, Hellebrand S, Wunderlich H-J. Efficient Consistency Checking for Embedded Memories. 10th GI/ITG/GMM/IEEE Workshop; 1998.
LibreCat: /record/13092

Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. In: Mixed-Mode BIST Using Embedded Processors. 5. Kluwer Academic Publishers; 1998.
LibreCat: /record/13060

Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. Journal of Electronic Testing Theory and Applications - JETTA. 1998;12(1/2):127-138.
LibreCat: /record/13061

Hellebrand S, Hertwig A, Wunderlich H-J. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. IEEE Design and Test. 1998;15(4):36-41.
LibreCat: /record/13064

Hertwig A, Hellebrand S, Wunderlich H-J. Fast Self-Recovering Controllers. In: 16th IEEE VLSI Test Symposium (VTS’98). IEEE; 1998:296-302. doi:10.1109/vtest.1998.670883
LibreCat: /record/13007
DOI: 10.1109/vtest.1998.670883

Hellebrand S, Wunderlich H-J, N. Yarmolik V. Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. In: Design Automation and Test in Europe (DATE’98). ; 1998:173-179. doi:10.1109/date.1998.655853
LibreCat: /record/13008
DOI: 10.1109/date.1998.655853

N. Yarmolik V, V. Klimets Y, Hellebrand S, Wunderlich H-J. New Transparent RAM BIST Based on Self-Adjusting Output Data Compression. In: Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’98). ; 1998:27-33.
LibreCat: /record/13063

Tsai K-H, Hellebrand S, Rajski J, Marek-Sadowska M. STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA; 1997.
LibreCat: /record/13089

Hertwig A, Hellebrand S, Wunderlich H-J. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 3rd IEEE International On-Line Testing Workshop, Crete, Greece; 1997.
LibreCat: /record/13090

Tsai K-H, Hellebrand S, Marek-Sadowska M, Rajski J. STARBIST: Scan Autocorrelated Random Pattern Generation. In: 34th ACM/IEEE Design Automation Conference (DAC’97). IEEE; 1997. doi:10.1109/dac.1997.597194
LibreCat: /record/13009
DOI: 10.1109/dac.1997.597194

Hellebrand S, Wunderlich H-J. Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA; 1996.
LibreCat: /record/13087

Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France; 1996.
LibreCat: /record/13088

Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. In: IEEE International Test Conference (ITC’96). IEEE; 1996:195-204. doi:10.1109/test.1996.556962
LibreCat: /record/13010
DOI: 10.1109/test.1996.556962

Hellebrand S, Wunderlich H-J. Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany; 1995.
LibreCat: /record/13026

Hellebrand S, Wunderlich H-J, Goncalves F, Paulo Teixeira J. Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany; 1995.
LibreCat: /record/13027

Hellebrand S, Herzog M, Wunderlich H-J. Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany; 1995.
LibreCat: /record/13028

Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J. Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA; 1995.
LibreCat: /record/13086

Hellebrand S, Rajski J, Tarnick S, Venkataraman S, Courtois B. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Transactions on Computers. 1995;44(2):223-233. doi:10.1109/12.364534
LibreCat: /record/13011
DOI: 10.1109/12.364534

Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J. Pattern Generation for a Deterministic BIST Scheme. In: ACM/IEEE International Conference on Computer Aided Design (ICCAD’95). IEEE; 1995:88-94. doi:10.1109/iccad.1995.479997
LibreCat: /record/13012
DOI: 10.1109/iccad.1995.479997

Hellebrand S, Juergensen A, Wunderlich H-J. Synthesis for Off-Line Testability. University of Siegen, Germany; 1994.
LibreCat: /record/13024

Hellebrand S, Juergensen A, Stroele A, Wunderlich H-J. Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany; 1994.
LibreCat: /record/13025

Venkataraman S, Rajski J, Hellebrand S, Tarnick S. Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands; 1994.
LibreCat: /record/13083

Hellebrand S, Wunderlich H-J. Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands; 1994.
LibreCat: /record/13084

Hellebrand S, Paulo Teixeira J, Wunderlich H-J. Synthesis for Testability - the ARCHIMEDES Approach. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA; 1994.
LibreCat: /record/13085

Hellebrand S, Wunderlich H-J. An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. In: ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94). IEEE; 1994:110-116. doi:10.1109/iccad.1994.629752
LibreCat: /record/13014
DOI: 10.1109/iccad.1994.629752

Hellebrand S, Wunderlich H-J. Synthese schneller selbsttestbarer Steuerwerke. In: Tagungsband Der GI/GME/ITG-Fachtagung \'26; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme. ; 1994:3-11.
LibreCat: /record/13059

Hellebrand S, Wunderlich H-J. Synthesis of Self-Testable Controllers. In: European Design and Test Conference (EDAC/ETC/EUROASIC). ; 1994:580-585. doi:10.1109/edtc.1994.326815
LibreCat: /record/13013
DOI: 10.1109/edtc.1994.326815

Hellebrand S, Tarnick S, Rajski J, Courtois B. Effiziente Erzeugung Deterministischer Muster Im Selbsttest. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany; 1993.
LibreCat: /record/13081

Hellebrand S, Wunderlich H-J. Synthesis of Self-Testable Controllers. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France; 1993.
LibreCat: /record/13082

Venkataraman S, Rajski J, Hellebrand S, Tarnick S. An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers. In: ACM/IEEE International Conference on Computer Aided Design (ICCAD’93). IEEE; 1993. doi:10.1109/iccad.1993.580117
LibreCat: /record/13015
DOI: 10.1109/iccad.1993.580117

Hellebrand S, Tarnick S, Rajski J, Courtois B. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Institut National Polytechnique de Grenoble, Grenoble, France; 1992.
LibreCat: /record/13023

Hellebrand S, Tarnick S, Rajski J, Courtois B. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. IEEE Design for Testability Workshop, Vail, CO, USA; 1992.
LibreCat: /record/13076

Hellebrand S, Tarnick S, Rajski J, Courtois B. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Workshop on New Directions for Testing, Montreal, Canada; 1992.
LibreCat: /record/13080

Wunderlich H-J, Hellebrand S. The Pseudoexhaustive Test of Sequential Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 1992;11(1):26-33. doi:10.1109/43.108616
LibreCat: /record/13017
DOI: 10.1109/43.108616

Hellebrand S, Tarnick S, Rajski J, Courtois B. Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. In: IEEE International Test Conference (ITC’92). IEEE; 1992:120-129. doi:10.1109/test.1992.527812
LibreCat: /record/13016
DOI: 10.1109/test.1992.527812

Hellebrand S. Synthese Vollständig Testbarer Schaltungen. Verlag Düsseldorf: VDI Verlag: Verlag Düsseldorf: VDI Verlag; 1991.
LibreCat: /record/13034

Hellebrand S, Wunderlich H-J, F. Haberl O. Generating Pseudo-Exhaustive Vectors for External Testing. IEEE Design for Testability Workshop, Vail, CO, USA; 1990.
LibreCat: /record/13103

Hellebrand S, Wunderlich H-J. Tools and Devices Supporting the Pseudo-Exhaustive Test. In: European Design Automation Conference (EDAC’90). IEEE; 1990:13-17. doi:10.1109/edac.1990.136612
LibreCat: /record/13018
DOI: 10.1109/edac.1990.136612

Hellebrand S, Wunderlich H-J, F. Haberl O. Generating Pseudo-Exhaustive Vectors for External Testing. In: IEEE International Test Conference (ITC’90). IEEE; 1990:670-679. doi:10.1109/test.1990.114082
LibreCat: /record/13019
DOI: 10.1109/test.1990.114082

Wunderlich H-J, Hellebrand S. The Pseudo-Exhaustive Test of Sequential Circuits. In: IEEE International Test Conference (ITC’89). IEEE; 1989:19-27. doi:10.1109/test.1989.82273
LibreCat: /record/13020
DOI: 10.1109/test.1989.82273

Wunderlich H-J, Hellebrand S. Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits. In: 18th International Symposium on Fault-Tolerant Computing, FTCS-18. ; 1988:36-45. doi:10.1109/ftcs.1988.5294
LibreCat: /record/13021
DOI: 10.1109/ftcs.1988.5294

Schmid D, Wunderlich H-J, Feldbusch F, Hellebrand S, Holzinger J, Kunzmann A. Integrated Tools for Automatic Design for Testability. In: Tool Integration and Design Environments, F.J. Rammig (Editor). Amsterdam: Elsevier Science Publishers B.V.(North Holland), IFIP; 1988:233-258.
LibreCat: /record/13058

Hellebrand S, Wunderlich H-J. Automatisierung des Entwurfs vollständig testbarer Schaltungen. In: GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188. Springer Verlag; 1988:145-159.
LibreCat: /record/13062

Hellebrand S. Deformation Dicker Punkte Und Netze von Quadriken. Universität Regensburg, Fakultät für Mathematik, Regensburg, Germany; 1986.
LibreCat: /record/13022