Hunger, Marc, and Sybille Hellebrand. “Ausbeute Und Fehlertoleranz Bei Dreifach Modularer Redundanz.” 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2010, pp. 81–88.
LibreCat: /record/13051

Hellebrand, Sybille. Nano-Electronic Systems. 2010.
LibreCat: /record/13073

Hopsch, Fabian, et al. “Variation-Aware Fault Modeling.”10.1109/ats.2010.24__19th IEEE Asian Test Symposium (ATS’10), IEEE, 2010, pp. 87–93, doi:10.1109/ats.2010.24.
LibreCat: /record/12983
DOI: 10.1109/ats.2010.24

Indlekofer, Thomas, et al. “Efficient Test Response Compaction for Robust BIST Using Parity Sequences.”10.1109/iccd.2010.5647648__28th IEEE International Conference on Computer Design (ICCD’10), IEEE, 2010, pp. 480–85, doi:10.1109/iccd.2010.5647648.
LibreCat: /record/12985
DOI: 10.1109/iccd.2010.5647648

Hunger, Marc, and Sybille Hellebrand. “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems.”10.1109/dft.2010.19__25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), IEEE, 2010, pp. 101–08, doi:10.1109/dft.2010.19.
LibreCat: /record/12986
DOI: 10.1109/dft.2010.19

Froese, Viktor, et al. “Reusing NoC-Infrastructure for Test Data Compression.”10.1109/vts.2010.5469570__28th IEEE VLSI Test Symposium (VTS’10), IEEE, 2010, pp. 227–31, doi:10.1109/vts.2010.5469570.
LibreCat: /record/12988
DOI: 10.1109/vts.2010.5469570

Becker, Bernd, et al. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper), 2010.
LibreCat: /record/13049

Indlekofer, Thomas, et al. “Robuster Selbsttest Mit Extremer Kompaktierung.” 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2010, pp. 17–24.
LibreCat: /record/13050

Hunger, Marc, et al. “ATPG-Based Grading of Strong Fault-Secureness.”10.1109/iolts.2009.5196027__15th IEEE International On-Line Testing Symposium (IOLTS’09, IEEE, 2009, doi:10.1109/iolts.2009.5196027.
LibreCat: /record/12991
DOI: 10.1109/iolts.2009.5196027

Hellebrand, Sybille, and Marc Hunger. “Are Robust Circuits Really Robust?”10.1109/dft.2009.28__24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, 2009, p. 77, doi:10.1109/dft.2009.28.
LibreCat: /record/12990
DOI: 10.1109/dft.2009.28

Hunger, Marc, et al. “Robustheitsanalyse Stark Fehlersicherer Schaltungen Mit SAT-Basierter Testmustererzeugung.” 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2009.
LibreCat: /record/13030

Coym, Torsten, et al. Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit. 2008.
LibreCat: /record/13033

Amgalan, Uranmandakh, et al. Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen. 2008.
LibreCat: /record/13035

Oehler, Philipp, et al. “A Modular Memory BIST for Optimized Memory Repair.”10.1109/iolts.2008.30__14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster), IEEE, 2008, doi:10.1109/iolts.2008.30.
LibreCat: /record/12992
DOI: 10.1109/iolts.2008.30

Amgalan, Uranmandakh, et al. “Signature Rollback - A Technique for Testing Robust Circuits.”10.1109/vts.2008.34__26th IEEE VLSI Test Symposium (VTS’08), IEEE, 2008, pp. 125–30, doi:10.1109/vts.2008.34.
LibreCat: /record/12994
DOI: 10.1109/vts.2008.34

Hunger, Marc, and Sybille Hellebrand. “Verification and Analysis of Self-Checking Properties through ATPG.”10.1109/iolts.2008.32__14th IEEE International On-Line Testing Symposium (IOLTS’08), IEEE, 2008, doi:10.1109/iolts.2008.32.
LibreCat: /record/12993
DOI: 10.1109/iolts.2008.32

Hunger, Marc, and Sybille Hellebrand. “Analyse Selbstprüfender Schaltungen – Nachweis von Fehlersicherheit Und Selbsttestbarkeit Mit ATPG.” 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2008.
LibreCat: /record/13031

Oehler, Philipp, et al. “Modularer Selbsttest Und Optimierte Reparaturanalyse.” 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2008.
LibreCat: /record/13032

Hellebrand, Sybille. Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 2007.
LibreCat: /record/13038

Ali, Muhammad, et al. An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. 2007.
LibreCat: /record/13039

Oehler, Philipp, et al. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 2007.
LibreCat: /record/13042

Hellebrand, Sybille. Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden. 2007.
LibreCat: /record/13043

Hellebrand, Sybille, et al. “A Refined Electrical Model for Particle Strikes and Its Impact on SEU Prediction.”10.1109/dft.2007.43__22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), IEEE, 2007, pp. 50–58, doi:10.1109/dft.2007.43.
LibreCat: /record/12995
DOI: 10.1109/dft.2007.43

Oehler, Philipp, et al. “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.”10.1109/ddecs.2007.4295278__10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), IEEE, 2007, pp. 185–90, doi:10.1109/ddecs.2007.4295278.
LibreCat: /record/12996
DOI: 10.1109/ddecs.2007.4295278

Oehler, Philipp, et al. “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.”10.1109/ets.2007.10__12th IEEE European Test Symposium (ETS’07), IEEE, 2007, pp. 91–96, doi:10.1109/ets.2007.10.
LibreCat: /record/12997
DOI: 10.1109/ets.2007.10

Hellebrand, Sybille, et al. “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance.” 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper), 2007.
LibreCat: /record/13037

Hellebrand, Sybille, et al. “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance.” Informacije MIDEM, Ljubljana (Invited Paper), vol. 37, no. 4 (124), 2007, pp. 212–19.
LibreCat: /record/13036

Ali, Muhammad, et al. “An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip.” International Journal on High Performance Systems Architecture, vol. 1, no. 2, 2007, pp. 113–23.
LibreCat: /record/13044

Ali, Muhammad, et al. “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip.” 4th International Conference on Information Technology: New Generations (ITNG’07), 2007, pp. 1027–32.
LibreCat: /record/13040

Becker, Bernd, et al. “Test Und Zuverlässigkeit Nanoelektronischer Systeme.” 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2007.
LibreCat: /record/13041

Becker, Bernd, et al. “DFG-Projekt RealTest - Test Und Zuverlässigkeit Nanoelektronischer Systeme.” It - Information Technology, vol. 48, no. 5, 2006, pp. 305–11.
LibreCat: /record/13045

Oehler, Philipp, and Sybille Hellebrand. A Low Power Design for Embedded DRAMs with Online Consistency Checking. 2005.
LibreCat: /record/13046

Ali, Muhammad, et al. Dynamic Routing: A Prerequisite for Reliable NoCs. 2005.
LibreCat: /record/13101

Oehler, Philipp, and Sybille Hellebrand. Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 2005.
LibreCat: /record/13102

Ali, Muhammad, et al. “Considerations for Fault-Tolerant Networks on Chips.”10.1109/icm.2005.1590063__IEEE International Conference on Microelectronics (ICM’05), IEEE, 2005, doi:10.1109/icm.2005.1590063.
LibreCat: /record/12999
DOI: 10.1109/icm.2005.1590063

Oehler, Philipp, and Sybille Hellebrand. “Low Power Embedded DRAMs with High Quality Error Correcting Capabilities.”10.1109/ets.2005.28__10th IEEE European Test Symposium (ETS’05), IEEE, 2005, pp. 148–53, doi:10.1109/ets.2005.28.
LibreCat: /record/13000
DOI: 10.1109/ets.2005.28

Ali, Muhammad, et al. “A Dynamic Routing Mechanism for Network on Chip.”10.1109/norchp.2005.1596991__23rd IEEE NORCHIP Conference, IEEE, 2005, pp. 70–73, doi:10.1109/norchp.2005.1596991.
LibreCat: /record/12998
DOI: 10.1109/norchp.2005.1596991

Liu Jing, Michelle, et al. “Sensor Networks with More Features Using Less Hardware.” GOR/NGB Conference Tilburg 2004, 2004.
LibreCat: /record/13071

Breu, Ruth, et al. Im Westen Viel Neues - Informatik an Der Universität Innsbruck. 2004.
LibreCat: /record/13099

Hellebrand, Sybille, et al. Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 2004.
LibreCat: /record/13100

Wuertenberger, Armin, et al. “Data Compression for Multiple Scan Chains Using Dictionaries with Corrections.”10.1109/test.2004.1387357__IEEE International Test Conference (ITC’04), IEEE, 2004, pp. 926–35, doi:10.1109/test.2004.1387357.
LibreCat: /record/13001
DOI: 10.1109/test.2004.1387357

Breu, Ruth, et al. Experiences from Teaching Software Development in a Java Environment. 2003.
LibreCat: /record/13098

Wuertenberger, Armin, et al. “A Hybrid Coding Strategy for Optimized Test Data Compression.”10.1109/test.2003.1270870__IEEE International Test Conference (ITC’03), IEEE, 2003, pp. 451–59, doi:10.1109/test.2003.1270870.
LibreCat: /record/13002
DOI: 10.1109/test.2003.1270870

Hellebrand, Sybille, and Armin Wuertenberger. Alternating Run-Length Coding: A Technique for Improved Test Data Compression. 2002.
LibreCat: /record/13097

Hellebrand, Sybille, et al. “Efficient Online and Offline Testing of Embedded DRAMs.”10.1109/tc.2002.1017700__IEEE Transactions on Computers, vol. 51, no. 7, IEEE, 2002, pp. 801–09, doi:10.1109/tc.2002.1017700.
LibreCat: /record/13003
DOI: 10.1109/tc.2002.1017700

Hellebrand, Sybille, et al. “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 18, no. 2, 2002, pp. 157–68.
LibreCat: /record/13069

Liang, Huaguo, et al. “A Mixed-Mode BIST Scheme Based on Folding Compression.” Journal on Computer Science and Technology, vol. 17, no. 2, 2002, pp. 203–12.
LibreCat: /record/13070

Liang, Hua-Guo, et al. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. 2001.
LibreCat: /record/13096

Liang, Hua-Guo, et al. “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.”10.1109/test.2001.966712__IEEE International Test Conference (ITC’01), IEEE, 2001, pp. 894–902, doi:10.1109/test.2001.966712.
LibreCat: /record/13004
DOI: 10.1109/test.2001.966712

Liang, Hua-Guo, et al. “Deterministic BIST Scheme Based on Reseeding of Folding Counters.” Journal of Computer Research and Development, (Jisuanji Yanjiu Yu Fazhan), vol. 38, no. 8, 2001, p. 931.
LibreCat: /record/13047

Hellebrand, Sybille, et al. “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 17, no. 3/4, 2001, pp. 341–49.
LibreCat: /record/13068

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Hardwarepraktikum Im Diplomstudiengang Informatik. 2000.
LibreCat: /record/13094

Hellebrand, Sybille, et al. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. 2000.
LibreCat: /record/13095

Hellebrand, Sybille, et al. “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.”10.1109/test.2000.894274__IEEE International Test Conference (ITC’00), IEEE, 2000, pp. 778–84, doi:10.1109/test.2000.894274.
LibreCat: /record/13005
DOI: 10.1109/test.2000.894274

Hellebrand, Sybille. Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren. Verlag Dr. Kovac, Hamburg, 1999.
LibreCat: /record/13065

Hellebrand, Sybille, et al. Exploiting Symmetries to Speed Up Transparent BIST. 1999.
LibreCat: /record/13093

Hellebrand, Sybille, et al. “Error Detecting Refreshment for Embedded DRAMs.”10.1109/vtest.1999.766693__17th IEEE VLSI Test Symposium (VTS’99), IEEE, 1999, pp. 384–90, doi:10.1109/vtest.1999.766693.
LibreCat: /record/13006
DOI: 10.1109/vtest.1999.766693

N. Yarmolik, Vyacheslav, et al. “Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.” Third European Dependable Computing Conference (EDCC-3), 1999.
LibreCat: /record/13066

Hellebrand, Sybille, et al. “Symmetric Transparent BIST for RAMs.” Design Automation and Test in Europe (DATE’99), 1999, pp. 702–07.
LibreCat: /record/13067

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Test Und Synthese Schneller Eingebetteter Systeme. 1998.
LibreCat: /record/13029

N. Yarmolik, Vyacheslav, et al. Efficient Consistency Checking for Embedded Memories. 1998.
LibreCat: /record/13091

N. Yarmolik, Vyacheslav, et al. Efficient Consistency Checking for Embedded Memories. 1998.
LibreCat: /record/13092

Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.” Mixed-Mode BIST Using Embedded Processors, Kluwer Academic Publishers, 1998.
LibreCat: /record/13060

Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.” Journal of Electronic Testing Theory and Applications - JETTA, vol. 12, no. 1/2, 1998, pp. 127–38.
LibreCat: /record/13061

Hellebrand, Sybille, et al. “Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications.” IEEE Design and Test, vol. 15, no. 4, IEEE, 1998, pp. 36–41.
LibreCat: /record/13064

Hertwig, Andre, et al. “Fast Self-Recovering Controllers.”10.1109/vtest.1998.670883__16th IEEE VLSI Test Symposium (VTS’98), IEEE, 1998, pp. 296–302, doi:10.1109/vtest.1998.670883.
LibreCat: /record/13007
DOI: 10.1109/vtest.1998.670883

Hellebrand, Sybille, et al. “Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.”10.1109/date.1998.655853__Design Automation and Test in Europe (DATE’98), 1998, pp. 173–79, doi:10.1109/date.1998.655853.
LibreCat: /record/13008
DOI: 10.1109/date.1998.655853

N. Yarmolik, Vyacheslav, et al. “New Transparent RAM BIST Based on Self-Adjusting Output Data Compression.” Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’98), 1998, pp. 27–33.
LibreCat: /record/13063

Tsai, Kun-Han, et al. STARBIST: Scan Autocorrelated Random Pattern Generation. 1997.
LibreCat: /record/13089

Hertwig, Andre, et al. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 1997.
LibreCat: /record/13090

Tsai, Kun-Han, et al. “STARBIST: Scan Autocorrelated Random Pattern Generation.”10.1109/dac.1997.597194__34th ACM/IEEE Design Automation Conference (DAC’97), IEEE, 1997, doi:10.1109/dac.1997.597194.
LibreCat: /record/13009
DOI: 10.1109/dac.1997.597194

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Using Embedded Processors for BIST. 1996.
LibreCat: /record/13087

Hellebrand, Sybille, et al. Mixed-Mode BIST Using Embedded Processors. 1996.
LibreCat: /record/13088

Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.”10.1109/test.1996.556962__IEEE International Test Conference (ITC’96), IEEE, 1996, pp. 195–204, doi:10.1109/test.1996.556962.
LibreCat: /record/13010
DOI: 10.1109/test.1996.556962

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Synthesis Procedures for Self-Testable Controllers. 1995.
LibreCat: /record/13026

Hellebrand, Sybille, et al. Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. 1995.
LibreCat: /record/13027

Hellebrand, Sybille, et al. Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. 1995.
LibreCat: /record/13028

Hellebrand, Sybille, et al. Pattern Generation for a Deterministic BIST Scheme. 1995.
LibreCat: /record/13086

Hellebrand, Sybille, et al. “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.”10.1109/12.364534__IEEE Transactions on Computers, vol. 44, no. 2, IEEE, 1995, pp. 223–33, doi:10.1109/12.364534.
LibreCat: /record/13011
DOI: 10.1109/12.364534

Hellebrand, Sybille, et al. “Pattern Generation for a Deterministic BIST Scheme.”10.1109/iccad.1995.479997__ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), IEEE, 1995, pp. 88–94, doi:10.1109/iccad.1995.479997.
LibreCat: /record/13012
DOI: 10.1109/iccad.1995.479997

Hellebrand, Sybille, et al. Synthesis for Off-Line Testability. 1994.
LibreCat: /record/13024

Hellebrand, Sybille, et al. Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. 1994.
LibreCat: /record/13025

Venkataraman, Srikanth, et al. Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen. 1994.
LibreCat: /record/13083

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese. 1994.
LibreCat: /record/13084

Hellebrand, Sybille, et al. Synthesis for Testability - the ARCHIMEDES Approach. 1994.
LibreCat: /record/13085

Hellebrand, Sybille, and Hans-Joachim Wunderlich. “An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures.”10.1109/iccad.1994.629752__ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), IEEE, 1994, pp. 110–16, doi:10.1109/iccad.1994.629752.
LibreCat: /record/13014
DOI: 10.1109/iccad.1994.629752

Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthese Schneller Selbsttestbarer Steuerwerke.” Tagungsband Der GI/GME/ITG-Fachtagung \'26; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, 1994, pp. 3–11.
LibreCat: /record/13059

Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthesis of Self-Testable Controllers.”10.1109/edtc.1994.326815__European Design and Test Conference (EDAC/ETC/EUROASIC), 1994, pp. 580–85, doi:10.1109/edtc.1994.326815.
LibreCat: /record/13013
DOI: 10.1109/edtc.1994.326815

Hellebrand, Sybille, et al. Effiziente Erzeugung Deterministischer Muster Im Selbsttest. 1993.
LibreCat: /record/13081

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Synthesis of Self-Testable Controllers. 1993.
LibreCat: /record/13082

Venkataraman, Srikanth, et al. “An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers.”10.1109/iccad.1993.580117__ACM/IEEE International Conference on Computer Aided Design (ICCAD’93), IEEE, 1993, doi:10.1109/iccad.1993.580117.
LibreCat: /record/13015
DOI: 10.1109/iccad.1993.580117

Hellebrand, Sybille, et al. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. 1992.
LibreCat: /record/13023

Hellebrand, Sybille, et al. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. 1992.
LibreCat: /record/13076

Hellebrand, Sybille, et al. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. 1992.
LibreCat: /record/13080

Wunderlich, Hans-Joachim, and Sybille Hellebrand. “The Pseudoexhaustive Test of Sequential Circuits.”10.1109/43.108616__IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 11, no. 1, Institute of Electrical and Electronics Engineers (IEEE), 1992, pp. 26–33, doi:10.1109/43.108616.
LibreCat: /record/13017
DOI: 10.1109/43.108616

Hellebrand, Sybille, et al. “Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.”10.1109/test.1992.527812__IEEE International Test Conference (ITC’92), IEEE, 1992, pp. 120–29, doi:10.1109/test.1992.527812.
LibreCat: /record/13016
DOI: 10.1109/test.1992.527812

Hellebrand, Sybille. Synthese Vollständig Testbarer Schaltungen. Verlag Düsseldorf: VDI Verlag, 1991.
LibreCat: /record/13034

Hellebrand, Sybille, et al. Generating Pseudo-Exhaustive Vectors for External Testing. 1990.
LibreCat: /record/13103

Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Tools and Devices Supporting the Pseudo-Exhaustive Test.”10.1109/edac.1990.136612__European Design Automation Conference (EDAC’90), IEEE, 1990, pp. 13–17, doi:10.1109/edac.1990.136612.
LibreCat: /record/13018
DOI: 10.1109/edac.1990.136612

Hellebrand, Sybille, et al. “Generating Pseudo-Exhaustive Vectors for External Testing.”10.1109/test.1990.114082__IEEE International Test Conference (ITC’90), IEEE, 1990, pp. 670–79, doi:10.1109/test.1990.114082.
LibreCat: /record/13019
DOI: 10.1109/test.1990.114082