Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., &; Wunderlich, H.-J. (n.d.). Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. European Test Symposium, The Hague, Netherlands, May 20-24, 2024, 6.

Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., &; Wunderlich, H.-J. (n.d.). Vmin Testing under Variations: Defect vs. Fault Coverage. IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, 6.

Hellebrand, S., Sadeghi-Kohan, S., &; Wunderlich, H.-J. (n.d.). Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.

Wunderlich, H.-J., Jafarzadeh, H., &; Hellebrand, S. (n.d.). Robust Test of Small Delay Faults under  PVT-Variations. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.

Stiballe, A., Reimer, J. D., Sadeghi-Kohan, S., &; Hellebrand, S. (2024). Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024.

Ghazal, A., Sadeghi-Kohan, S., Reimer, J. D., &; Hellebrand, S. (2023). On Cryptography Effects on Interconnect Reliability. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023.

Sprenger, A. (2023). Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Universität Paderborn.https://doi.org/10.17619/UNIPB/1-1787 

Sadeghi-Kohan, S., Hellebrand, S., &; Wunderlich, H.-J. (2023). Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W).https://doi.org/10.1109/dsn-w58399.2023.00056 

Sadeghi-Kohan, S., Reimer, J. D., Hellebrand, S., &; Wunderlich, H.-J. (2023). Optimizing the Streaming of Sensor Data with Approximate Communication. IEEE Asian Test Symposium (ATS’23), October 2023. IEEE Asian Test Symposium (ATS’23).

Sadeghi-Kohan, S., Hellebrand, S., &; Wunderlich, H.-J. (2023). Workload-Aware Periodic Interconnect BIST. IEEE Design &;Test, 1–1.https://doi.org/10.1109/mdat.2023.3298849 

Jafarzadeh, H., Klemme, F., Reimer, J. D., Najafi Haghi, Z. P.,  Amrouch, H., Hellebrand, S., &;  Wunderlich, H.-J. (2023). Robust Pattern Generation for Small Delay Faults under Process Variations. IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE International Test Conference (ITC’23), Anaheim, USA.

Sadeghi-Kohan, S., Hellebrand, S., &; Wunderlich, H.-J. (2022). Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing.https://doi.org/10.1007/s10836-021-05979-5 

Sadeghi-Kohan, S., Hellebrand, S., &; Wunderlich, H.-J. (2022). EM-Aware Interconnect BIST. European Workshop on Silicon Lifecycle Management, March 18, 2022.

Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., &; Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020.

Sadeghi-Kohan, S., &; Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020.

Sadeghi-Kohan, S., &; Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 38th IEEE VLSI Test Symposium (VTS).https://doi.org/10.1109/vts48691.2020.9107591 

Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich, H.-J., &; Weng, X. (2020). Logic Fault Diagnosis of Hidden Delay Defects. IEEE International Test Conference (ITC’20), November 2020.

Maaz, M. U., Sprenger, A., &; Hellebrand, S. (2019). A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19).

Sprenger, A., &; Hellebrand, S. (2019). Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers, 28(1), 1–23.https://doi.org/10.1142/s0218126619400012 

Kampmann, M., A. Kochte, M., Liu, C., Schneider, E., Hellebrand, S., &; Wunderlich, H.-J. (2019). Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(10), 1956–1968.

Maaz, M. U., Sprenger, A., &; Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. 50th IEEE International Test Conference (ITC), 1–8.

Sprenger, A., &; Hellebrand, S. (2018). Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18).

Hellebrand, S., Henkel, J., Raghunathan, A., &; Wunderlich, H.-J. (2018). Guest Editors’ Introduction - Special Issue on Approximate Computing. IEEE Embedded Systems Letters, 10(1), 1–1.https://doi.org/10.1109/les.2018.2789942 

Kampmann, M., &; Hellebrand, S. (2018). Design For Small Delay Test - A Simulation Study. Microelectronics Reliability, 80, 124–133.

Kampmann, M., &; Hellebrand, S. (2018). Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China.

Rezaeizadeh Rookerd, R., Sadeghi-Kohan, S., &; Navabi, Z. (2018). Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. Proceedings of the 2018 on Great Lakes Symposium on VLSI.https://doi.org/10.1145/3194554.3194599 

Sprenger, A., &; Hellebrand, S. (2018). Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &; Systems (DDECS).https://doi.org/10.1109/ddecs.2018.00020 

Liu, C., Schneider, E., Kampmann, M., Hellebrand, S., &; Wunderlich, H.-J. (2018). Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. 27th IEEE Asian Test Symposium (ATS’18).https://doi.org/10.1109/ats.2018.00028 

Sadeghi-Kohan, S., Vafaei, A., &; Navabi, Z. (2018). Near-Optimal Node Selection Procedure for Aging Monitor Placement. 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).https://doi.org/10.1109/iolts.2018.8474120 

Deshmukh, J., Kunz, W., Wunderlich, H.-J., &; Hellebrand, S. (2017). Special Session on Early Life Failures. In 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE.https://doi.org/10.1109/vts.2017.7928933 

Kampmann, M., &; Hellebrand, S. (2017). X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz.

Kampmann, M., &; Hellebrand, S. (2017). Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. 20th IEEE International Symposium on Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’17).https://doi.org/10.1109/ddecs.2017.7934564 

Sadeghi-Kohan, S., Kamal, M., &; Navabi, Z. (2017). Self-Adjusting Monitor for Measuring Aging Rate and Advancement. IEEE Transactions on Emerging Topics in Computing, 8(3), 627–641.https://doi.org/10.1109/tetc.2017.2771441 

Jenihhin, M., Kamkin, A., Navabi, Z., &; Sadeghi-Kohan, S. (2017). Universal mitigation of NBTI-induced aging by design randomization. 2016 IEEE East-West Design &; Test Symposium (EWDTS).https://doi.org/10.1109/ewdts.2016.7807635 

Kampmann, M., &; Hellebrand, S. (2016). X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. In 25th IEEE Asian Test Symposium (ATS’16) (pp. 1–6). Hiroshima, Japan: IEEE.https://doi.org/10.1109/ats.2016.20 

Kampmann, M., A. Kochte, M., Schneider, E., Indlekofer, T., Hellebrand, S., &; Wunderlich, H.-J. (2015). Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In 24th IEEE Asian Test Symposium (ATS’15) (pp. 109–114). Mumbai, India: IEEE.https://doi.org/10.1109/ats.2015.26 

Huang, Z., Liang, H., &; Hellebrand, S. (2015). A High Performance SEU Tolerant Latch. Journal of Electronic Testing - Theory and Applications (JETTA), 31(4), 349–359.

Hellebrand, S., Indlekofer, T., Kampmann, M., Kochte, M., Liu, C., &; Wunderlich, H.-J. (2015). Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany.

Sadeghi-Kohan, S., Kamran, A., Forooghifar, F., &; Navabi, Z. (2015). Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. 2015 10th International Conference on Design &; Technology of Integrated Systems in Nanoscale Era (DTIS).https://doi.org/10.1109/dtis.2015.7127373 

Sadeghi-Kohan, S., Kamal, M., McNeil, J., Prinetto, P., &; Navabi, Z. (2015). Online self adjusting progressive age monitoring of timing variations. 2015 10th International Conference on Design &; Technology of Integrated Systems in Nanoscale Era (DTIS).https://doi.org/10.1109/dtis.2015.7127368 

Hellebrand, S., Indlekofer, T., Kampmann, M., A. Kochte, M., Liu, C., &; Wunderlich, H.-J. (2014). FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In IEEE International Test Conference (ITC’14). Seattle, Washington, USA: IEEE.https://doi.org/10.1109/test.2014.7035360 

Hellebrand, S., &; Wunderlich, H.-J. (2014). SAT-Based ATPG beyond Stuck-at Fault Testing. DeGruyter Journal on Information Technology (It), 56(4), 165–172.

Rodriguez Gomez, L., Cook, A., Indlekofer, T., Hellebrand, S., &; Wunderlich, H.-J. (2014). Adaptive Bayesian Diagnosis of Intermittent Faults. Journal of Electronic Testing - Theory and Applications (JETTA), 30(5), 527–540.

Alizadeh, B., Behnam, P., &; Sadeghi-Kohan, S. (2014). A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers, 1–1.https://doi.org/10.1109/tc.2014.2329687 

Mohammadi, M., Sadeghi-Kohan, S., Masoumi, N., &; Navabi, Z. (2014). An off-line MDSI interconnect BIST incorporated in BS 1149.1. 2014 19th IEEE European Test Symposium (ETS).https://doi.org/10.1109/ets.2014.6847847 

Sadeghi-Kohan, S., Behnam, P., Alizadeh, B., Fujita, M., &; Navabi, Z. (2014). Improving polynomial datapath debugging with HEDs. 2014 19th IEEE European Test Symposium (ETS).https://doi.org/10.1109/ets.2014.6847797 

Hellebrand, S. (2013). Analyzing and Quantifying Fault Tolerance Properties. In 14th IEEE Latin American Test Workshop - (LATW’13). Cordoba, Argentina: IEEE.https://doi.org/10.1109/latw.2013.6562662 

Cook, A., Rodriguez Gomez, L., Hellebrand, S., Indlekofer, T., &; Wunderlich, H.-J. (2013). Adaptive Test and Diagnosis of Intermittent Faults. 14th Latin American Test Workshop, Cordoba, Argentina.

Sadeghi-Kohan, S., Namaki-Shoushtari, M., Javaheri, F., &; Navabi, Z. (2013). BS 1149.1 extensions for an online interconnect fault detection and recovery. 2012 IEEE International Test Conference.https://doi.org/10.1109/test.2012.6401583 

Sadeghi-Kohan, S., Keshavarz, S., Zokaee, F., Farahmandi, F., &; Navabi, Z. (2013). A new structure for interconnect offline testing. East-West Design &;amp; Test Symposium (EWDTS 2013).https://doi.org/10.1109/ewdts.2013.6673207 

Cook, A., Hellebrand, S., E. Imhof, M., Mumtaz, A., &; Wunderlich, H.-J. (2012). Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. In 13th IEEE Latin American Test Workshop (LATW’12) (pp. 1–4). Quito, Ecuador: IEEE.https://doi.org/10.1109/latw.2012.6261229 

Cook, A., Hellebrand, S., &; Wunderlich, H.-J. (2012). Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. In 17th IEEE European Test Symposium (ETS’12) (pp. 1–6). Annecy, France: IEEE.https://doi.org/10.1109/ets.2012.6233025 

Cook, A., Hellebrand, S., &; Wunderlich, H.-J. (2012). Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern. 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany.

Cook, A., Hellebrand, S., Indlekofer, T., &; Wunderlich, H.-J. (2011). Diagnostic Test of Robust Circuits. In 20th IEEE Asian Test Symposium (ATS’11) (pp. 285–290). New Delhi, India: IEEE.https://doi.org/10.1109/ats.2011.55 

Polian, I., Becker, B., Hellebrand, S., Wunderlich, H.-J., &; Maxwell, P. (2011). Towards Variation-Aware Test Methods. In 16th IEEE European Test Symposium Trondheim (ETS’11). Trondheim, Norway: IEEE.https://doi.org/10.1109/ets.2011.51 

Cook, A., Hellebrand, S., Indlekofer, T., &; Wunderlich, H.-J. (2011). Robuster Selbsttest mit Diagnose. In 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit und Entwurf” (pp. 48–53). Hamburg, Germany.

Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2011). Variation-Aware Fault Modeling. SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer, 54(4), 1813–1826.

Kamran, A., Nemati, N., Sadeghi-Kohan, S., &; Navabi, Z. (2011). Virtual tester development using HDL/PLI. 2010 East-West Design &;amp; Test Symposium (EWDTS).https://doi.org/10.1109/ewdts.2010.5742156 

Fröse, V., Ibers, R., &; Hellebrand, S. (2010). Testdatenkompression mit Hilfe der Netzwerkinfrastruktur. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany.

Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10). Chicago, IL, USA: IEEE.https://doi.org/10.1109/dsnw.2010.5542612 

Hunger, M., &; Hellebrand, S. (2010). Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf” (pp. 81–88). Wildbad Kreuth, Germany.

Hellebrand, S. (2010). Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180.

Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2010). Variation-Aware Fault Modeling. 19th IEEE Asian Test Symposium (ATS’10), 87–93.https://doi.org/10.1109/ats.2010.24 

Indlekofer, T., Schnittger, M., &; Hellebrand, S. (2010). Efficient Test Response Compaction for Robust BIST Using Parity Sequences. 28th IEEE International Conference on Computer Design (ICCD’10), 480–485.https://doi.org/10.1109/iccd.2010.5647648 

Hunger, M., &; Hellebrand, S. (2010). The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 101–108.https://doi.org/10.1109/dft.2010.19 

Froese, V., Ibers, R., &; Hellebrand, S. (2010). Reusing NoC-Infrastructure for Test Data Compression. 28th IEEE VLSI Test Symposium (VTS’10), 227–231.https://doi.org/10.1109/vts.2010.5469570 

Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper).

Indlekofer, T., Schnittger, M., &; Hellebrand, S. (2010). Robuster Selbsttest mit extremer Kompaktierung. 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 17–24.

Hunger, M., Hellebrand, S., Czutro, A., Polian, I., &; Becker, B. (2009). ATPG-Based Grading of Strong Fault-Secureness. 15th IEEE International On-Line Testing Symposium (IOLTS’09.https://doi.org/10.1109/iolts.2009.5196027 

Hellebrand, S., &; Hunger, M. (2009). Are Robust Circuits Really Robust? 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 77.https://doi.org/10.1109/dft.2009.28 

Hunger, M., Hellebrand, S., Czutro, A., Polian, I., &; Becker, B. (2009). Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”

Coym, T., Hellebrand, S., Ludwig, S., Straube, B., Wunderlich, H.-J., &; G. Zoellin, C. (2008). Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich.

Amgalan, U., Hachmann, C., Hellebrand, S., &; Wunderlich, H.-J. (2008). Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich.

Oehler, P., Bosio, A., di Natale, G., &; Hellebrand, S. (2008). A Modular Memory BIST for Optimized Memory Repair. 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster).https://doi.org/10.1109/iolts.2008.30 

Amgalan, U., Hachmann, C., Hellebrand, S., &; Wunderlich, H.-J. (2008). Signature Rollback - A Technique for Testing Robust Circuits. 26th IEEE VLSI Test Symposium (VTS’08), 125–130.https://doi.org/10.1109/vts.2008.34 

Hunger, M., &; Hellebrand, S. (2008). Verification and Analysis of Self-Checking Properties through ATPG. 14th IEEE International On-Line Testing Symposium (IOLTS’08).https://doi.org/10.1109/iolts.2008.32 

Hunger, M., &; Hellebrand, S. (2008). Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”

Oehler, P., Bosio, A., Di Natale, G., &; Hellebrand, S. (2008). Modularer Selbsttest und optimierte Reparaturanalyse. 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”

Hellebrand, S. (2007). Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 5th IEEE East-West Design \'26; Test Symposium, Yerevan, Armenia (Invited Talk).

Ali, M., Welzl, M., Hessler, S., &; Hellebrand, S. (2007). An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster).

Oehler, P., Hellebrand, S., &; Wunderlich, H.-J. (2007). An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany.

Hellebrand, S. (2007). Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany.

Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., &; Straube, B. (2007). A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), 50–58.https://doi.org/10.1109/dft.2007.43 

Oehler, P., Hellebrand, S., &; Wunderlich, H.-J. (2007). Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 185–190.https://doi.org/10.1109/ddecs.2007.4295278 

Oehler, P., Hellebrand, S., &; Wunderlich, H.-J. (2007). An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. 12th IEEE European Test Symposium (ETS’07), 91–96.https://doi.org/10.1109/ets.2007.10 

Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., &; Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper).

Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., &; Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. Informacije MIDEM, Ljubljana (Invited Paper), 37(4 (124)), 212–219.

Ali, M., Hessler, S., Welzl, M., &; Hellebrand, S. (2007). An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip. International Journal on High Performance Systems Architecture, 1(2), 113–123.

Ali, M., Welzl, M., Hessler, S., &; Hellebrand, S. (2007). A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip. 4th International Conference on Information Technology: New Generations (ITNG’07), 1027–1032.

Becker, B., Polian, I., Hellebrand, S., Straube, B., &; Wunderlich, H.-J. (2007). Test und Zuverlässigkeit nanoelektronischer Systeme. 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”

Becker, B., Polian, I., Hellebrand, S., Straube, B., &; Wunderlich, H.-J. (2006). DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme. It - Information Technology, 48(5), 305–311.

Oehler, P., &; Hellebrand, S. (2005). A Low Power Design for Embedded DRAMs with Online Consistency Checking. Kleinheubachertagung 2005, Miltenberg, Germany.

Ali, M., Welzl, M., &; Hellebrand, S. (2005). Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria.

Oehler, P., &; Hellebrand, S. (2005). Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria.

Ali, M., Welzl, M., Zwicknagl, M., &; Hellebrand, S. (2005). Considerations for Fault-Tolerant Networks on Chips. IEEE International Conference on Microelectronics (ICM’05).https://doi.org/10.1109/icm.2005.1590063 

Oehler, P., &; Hellebrand, S. (2005). Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. 10th IEEE European Test Symposium (ETS’05), 148–153.https://doi.org/10.1109/ets.2005.28 

Ali, M., Welzl, M., &; Hellebrand, S. (2005). A Dynamic Routing Mechanism for Network on Chip. 23rd IEEE NORCHIP Conference, 70–73.https://doi.org/10.1109/norchp.2005.1596991 

Liu Jing, M., Ruehrup, S., Schindelhauer, C., Volbert, K., Dierkes, M., Bellgardt, A.,  Hilleringmann, U. (2004). Sensor Networks with More Features Using Less Hardware. In GOR/NGB Conference Tilburg 2004. Tilburg, Netherlands.

Breu, R., Fahringer, T., Fensel, D., Hellebrand, S., Middeldorp, A., &; Scherzer, O. (2004). Im Westen viel Neues - Informatik an der Universität Innsbruck. OCG Journal, pp. 28-29.

Hellebrand, S., Wuertenberger, A., &; S. Tautermann, C. (2004). Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France.