Hellebrand, Sybille, et al. “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 17, no. 3/4, 2001, pp. 341–49.

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Hardwarepraktikum Im Diplomstudiengang Informatik. 2000.

Hellebrand, Sybille, et al. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. 2000.

Hellebrand, Sybille, et al. “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.”10.1109/test.2000.894274__IEEE International Test Conference (ITC’00), IEEE, 2000, pp. 778–84, doi:10.1109/test.2000.894274.

Hellebrand, Sybille. Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren. Verlag Dr. Kovac, Hamburg, 1999.

Hellebrand, Sybille, et al. Exploiting Symmetries to Speed Up Transparent BIST. 1999.

Hellebrand, Sybille, et al. “Error Detecting Refreshment for Embedded DRAMs.”10.1109/vtest.1999.766693__17th IEEE VLSI Test Symposium (VTS’99), IEEE, 1999, pp. 384–90, doi:10.1109/vtest.1999.766693.

N. Yarmolik, Vyacheslav, et al. “Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.” Third European Dependable Computing Conference (EDCC-3), 1999.

Hellebrand, Sybille, et al. “Symmetric Transparent BIST for RAMs.” Design Automation and Test in Europe (DATE’99), 1999, pp. 702–07.

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Test Und Synthese Schneller Eingebetteter Systeme. 1998.

N. Yarmolik, Vyacheslav, et al. Efficient Consistency Checking for Embedded Memories. 1998.

N. Yarmolik, Vyacheslav, et al. Efficient Consistency Checking for Embedded Memories. 1998.

Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.” Mixed-Mode BIST Using Embedded Processors, Kluwer Academic Publishers, 1998.

Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.” Journal of Electronic Testing Theory and Applications - JETTA, vol. 12, no. 1/2, 1998, pp. 127–38.

Hellebrand, Sybille, et al. “Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications.” IEEE Design and Test, vol. 15, no. 4, IEEE, 1998, pp. 36–41.

Hertwig, Andre, et al. “Fast Self-Recovering Controllers.”10.1109/vtest.1998.670883__16th IEEE VLSI Test Symposium (VTS’98), IEEE, 1998, pp. 296–302, doi:10.1109/vtest.1998.670883.

Hellebrand, Sybille, et al. “Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.”10.1109/date.1998.655853__Design Automation and Test in Europe (DATE’98), 1998, pp. 173–79, doi:10.1109/date.1998.655853.

N. Yarmolik, Vyacheslav, et al. “New Transparent RAM BIST Based on Self-Adjusting Output Data Compression.” Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’98), 1998, pp. 27–33.

Tsai, Kun-Han, et al. STARBIST: Scan Autocorrelated Random Pattern Generation. 1997.

Hertwig, Andre, et al. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 1997.

Tsai, Kun-Han, et al. “STARBIST: Scan Autocorrelated Random Pattern Generation.”10.1109/dac.1997.597194__34th ACM/IEEE Design Automation Conference (DAC’97), IEEE, 1997, doi:10.1109/dac.1997.597194.

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Using Embedded Processors for BIST. 1996.

Hellebrand, Sybille, et al. Mixed-Mode BIST Using Embedded Processors. 1996.

Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.”10.1109/test.1996.556962__IEEE International Test Conference (ITC’96), IEEE, 1996, pp. 195–204, doi:10.1109/test.1996.556962.

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Synthesis Procedures for Self-Testable Controllers. 1995.

Hellebrand, Sybille, et al. Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. 1995.

Hellebrand, Sybille, et al. Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. 1995.

Hellebrand, Sybille, et al. Pattern Generation for a Deterministic BIST Scheme. 1995.

Hellebrand, Sybille, et al. “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.”10.1109/12.364534__IEEE Transactions on Computers, vol. 44, no. 2, IEEE, 1995, pp. 223–33, doi:10.1109/12.364534.

Hellebrand, Sybille, et al. “Pattern Generation for a Deterministic BIST Scheme.”10.1109/iccad.1995.479997__ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), IEEE, 1995, pp. 88–94, doi:10.1109/iccad.1995.479997.

Hellebrand, Sybille, et al. Synthesis for Off-Line Testability. 1994.

Hellebrand, Sybille, et al. Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. 1994.

Venkataraman, Srikanth, et al. Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen. 1994.

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese. 1994.

Hellebrand, Sybille, et al. Synthesis for Testability - the ARCHIMEDES Approach. 1994.

Hellebrand, Sybille, and Hans-Joachim Wunderlich. “An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures.”10.1109/iccad.1994.629752__ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), IEEE, 1994, pp. 110–16, doi:10.1109/iccad.1994.629752.

Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthese Schneller Selbsttestbarer Steuerwerke.” Tagungsband Der GI/GME/ITG-Fachtagung \'26; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, 1994, pp. 3–11.

Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthesis of Self-Testable Controllers.”10.1109/edtc.1994.326815__European Design and Test Conference (EDAC/ETC/EUROASIC), 1994, pp. 580–85, doi:10.1109/edtc.1994.326815.

Hellebrand, Sybille, et al. Effiziente Erzeugung Deterministischer Muster Im Selbsttest. 1993.

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Synthesis of Self-Testable Controllers. 1993.

Venkataraman, Srikanth, et al. “An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers.”10.1109/iccad.1993.580117__ACM/IEEE International Conference on Computer Aided Design (ICCAD’93), IEEE, 1993, doi:10.1109/iccad.1993.580117.

Hellebrand, Sybille, et al. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. 1992.

Hellebrand, Sybille, et al. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. 1992.

Hellebrand, Sybille, et al. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. 1992.

Wunderlich, Hans-Joachim, and Sybille Hellebrand. “The Pseudoexhaustive Test of Sequential Circuits.”10.1109/43.108616__IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 11, no. 1, Institute of Electrical and Electronics Engineers (IEEE), 1992, pp. 26–33, doi:10.1109/43.108616.

Hellebrand, Sybille, et al. “Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.”10.1109/test.1992.527812__IEEE International Test Conference (ITC’92), IEEE, 1992, pp. 120–29, doi:10.1109/test.1992.527812.

Hellebrand, Sybille. Synthese Vollständig Testbarer Schaltungen. Verlag Düsseldorf: VDI Verlag, 1991.

Hellebrand, Sybille, et al. Generating Pseudo-Exhaustive Vectors for External Testing. 1990.

Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Tools and Devices Supporting the Pseudo-Exhaustive Test.”10.1109/edac.1990.136612__European Design Automation Conference (EDAC’90), IEEE, 1990, pp. 13–17, doi:10.1109/edac.1990.136612.

Hellebrand, Sybille, et al. “Generating Pseudo-Exhaustive Vectors for External Testing.”10.1109/test.1990.114082__IEEE International Test Conference (ITC’90), IEEE, 1990, pp. 670–79, doi:10.1109/test.1990.114082.

Wunderlich, Hans-Joachim, and Sybille Hellebrand. “The Pseudo-Exhaustive Test of Sequential Circuits.”10.1109/test.1989.82273__IEEE International Test Conference (ITC’89), IEEE, 1989, pp. 19–27, doi:10.1109/test.1989.82273.

Wunderlich, Hans-Joachim, and Sybille Hellebrand. “Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits.”10.1109/ftcs.1988.5294__18th International Symposium on Fault-Tolerant Computing, FTCS-18, 1988, pp. 36–45, doi:10.1109/ftcs.1988.5294.

Schmid, Detlef, et al. “Integrated Tools for Automatic Design for Testability.” Tool Integration and Design Environments, F.J. Rammig (Editor), Amsterdam: Elsevier Science Publishers B.V.(North Holland), IFIP, 1988, pp. 233–58.

Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Automatisierung Des Entwurfs Vollständig Testbarer Schaltungen.” GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188, Springer Verlag, 1988, pp. 145–59.

Hellebrand, Sybille. Deformation Dicker Punkte Und Netze von Quadriken. 1986.