Efficient Consistency Checking for Embedded Memories
V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories, 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1998.

Efficient Consistency Checking for Embedded Memories
V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories, 10th GI/ITG/GMM/IEEE Workshop, 1998.

Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: Mixed-Mode BIST Using Embedded Processors, Kluwer Academic Publishers, In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998, 1998.

Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, Journal of Electronic Testing Theory and Applications - JETTA 12 (1998) 127–138.

Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
S. Hellebrand, A. Hertwig, H.-J. Wunderlich, IEEE Design and Test 15 (1998) 36–41.

Fast Self-Recovering Controllers
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, in: 16th IEEE VLSI Test Symposium (VTS’98), IEEE, Monterey, CA, USA, 1998, pp. 296–302.

Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: Design Automation and Test in Europe (DATE’98), Paris, France, 1998, pp. 173–179.

New Transparent RAM BIST Based on Self-Adjusting Output Data Compression
V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, H.-J. Wunderlich, in: Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’98), Szczyrk, Poland, 1998, pp. 27–33.

STARBIST: Scan Autocorrelated Random Pattern Generation
K.-H. Tsai, S. Hellebrand, J. Rajski, M. Marek-Sadowska, STARBIST: Scan Autocorrelated Random Pattern Generation, 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1997.

Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications, 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.

STARBIST: Scan Autocorrelated Random Pattern Generation
K.-H. Tsai, S. Hellebrand, M. Marek-Sadowska, J. Rajski, in: 34th ACM/IEEE Design Automation Conference (DAC’97), IEEE, Anaheim, CA, USA, 1997.

Using Embedded Processors for BIST
S. Hellebrand, H.-J. Wunderlich, Using Embedded Processors for BIST, 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1996.

Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, Mixed-Mode BIST Using Embedded Processors, 2nd IEEE International On-Line Testing Workshop. Biarritz, France, 1996.

Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: IEEE International Test Conference (ITC’96), IEEE, Washington, DC, USA, 1996, pp. 195–204.

Synthesis Procedures for Self-Testable Controllers
S. Hellebrand, H.-J. Wunderlich, Synthesis Procedures for Self-Testable Controllers, University of Siegen, Germany, 1995.

Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis
S. Hellebrand, H.-J. Wunderlich, F. Goncalves, J. Paulo Teixeira, Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis, University Siegen, Germany, 1995.

Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing
S. Hellebrand, M. Herzog, H.-J. Wunderlich, Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing, University of Siegen, Germany, 1995.

Pattern Generation for a Deterministic BIST Scheme
S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, Pattern Generation for a Deterministic BIST Scheme, 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1995.

Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, IEEE Transactions on Computers 44 (1995) 223–233.

Pattern Generation for a Deterministic BIST Scheme
S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, in: ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), IEEE, San Jose, CA, USA, 1995, pp. 88–94.

Synthesis for Off-line Testability
S. Hellebrand, A. Juergensen, H.-J. Wunderlich, Synthesis for Off-Line Testability, University of Siegen, Germany, 1994.

Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time
S. Hellebrand, A. Juergensen, A. Stroele, H.-J. Wunderlich, Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time, University of Siegen, Germany, 1994.

Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen
S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick, Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen, 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.

Ein Verfahren zur testfreundlichen Steuerwerkssynthese
S. Hellebrand, H.-J. Wunderlich, Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese, 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.

Synthesis for Testability - the ARCHIMEDES Approach
S. Hellebrand, J. Paulo Teixeira, H.-J. Wunderlich, Synthesis for Testability - the ARCHIMEDES Approach, 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1994.

An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures
S. Hellebrand, H.-J. Wunderlich, in: ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), IEEE, San Jose, CA, USA, 1994, pp. 110–116.

Synthese schneller selbsttestbarer Steuerwerke
S. Hellebrand, H.-J. Wunderlich, in: Tagungsband Der GI/GME/ITG-Fachtagung \'26; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, Oberwiesenthal, Informatik Xpress 4, TU Chemnitz Zwickau, Germany, 1994, pp. 3–11.

Synthesis of Self-Testable Controllers
S. Hellebrand, H.-J. Wunderlich, in: European Design and Test Conference (EDAC/ETC/EUROASIC), Paris, France, 1994, pp. 580–585.

Effiziente Erzeugung deterministischer Muster im Selbsttest
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Effiziente Erzeugung Deterministischer Muster Im Selbsttest, 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany, 1993.

Synthesis of Self-Testable Controllers
S. Hellebrand, H.-J. Wunderlich, Synthesis of Self-Testable Controllers, ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France, 1993.

An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers
S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick, in: ACM/IEEE International Conference on Computer Aided Design (ICCAD’93), IEEE, 1993.

Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs, Institut National Polytechnique de Grenoble, Grenoble, France, 1992.

Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs, IEEE Design for Testability Workshop, Vail, CO, USA, 1992.

Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs, Workshop on New Directions for Testing, Montreal, Canada, 1992.

The Pseudoexhaustive Test of Sequential Circuits
H.-J. Wunderlich, S. Hellebrand, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 11 (1992) 26–33.

Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, in: IEEE International Test Conference (ITC’92), IEEE, Baltimore, MD, USA, 1992, pp. 120–129.

Synthese vollständig testbarer Schaltungen
S. Hellebrand, Synthese Vollständig Testbarer Schaltungen, Verlag Düsseldorf: VDI Verlag, Verlag Düsseldorf: VDI Verlag, 1991.

Generating Pseudo-Exhaustive Vectors for External Testing
S. Hellebrand, H.-J. Wunderlich, O. F. Haberl, Generating Pseudo-Exhaustive Vectors for External Testing, IEEE Design for Testability Workshop, Vail, CO, USA, 1990.

Tools and Devices Supporting the Pseudo-Exhaustive Test
S. Hellebrand, H.-J. Wunderlich, in: European Design Automation Conference (EDAC’90), IEEE, Glasgow, UK, 1990, pp. 13–17.

Generating Pseudo-Exhaustive Vectors for External Testing
S. Hellebrand, H.-J. Wunderlich, O. F. Haberl, in: IEEE International Test Conference (ITC’90), IEEE, Washington, DC, USA, 1990, pp. 670–679.

The Pseudo-Exhaustive Test of Sequential Circuits
H.-J. Wunderlich, S. Hellebrand, in: IEEE International Test Conference (ITC’89), IEEE, Washington, DC, USA, 1989, pp. 19–27.

Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits
H.-J. Wunderlich, S. Hellebrand, in: 18th International Symposium on Fault-Tolerant Computing, FTCS-18, Tokyo, Japan, 1988, pp. 36–45.

Integrated Tools for Automatic Design for Testability
D. Schmid, H.-J. Wunderlich, F. Feldbusch, S. Hellebrand, J. Holzinger, A. Kunzmann, in: Tool Integration and Design Environments, F.J. Rammig (Editor), Amsterdam: Elsevier Science Publishers B.V.(North Holland), IFIP, Amsterdam, The Netherlands, 1988, pp. 233–258.

Automatisierung des Entwurfs vollständig testbarer Schaltungen
S. Hellebrand, H.-J. Wunderlich, in: GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188, Springer Verlag, Hamburg, Germany, 1988, pp. 145–159.

Deformation dicker Punkte und Netze von Quadriken
S. Hellebrand, Deformation Dicker Punkte Und Netze von Quadriken, Universität Regensburg, Fakultät für Mathematik, Regensburg, Germany, 1986.