Cook A, Hellebrand S, E. Imhof M, Mumtaz A, Wunderlich H-J. Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. In: 13th IEEE Latin American Test Workshop (LATW’12). Quito, Ecuador: IEEE; 2012:1-4. doi:10.1109/latw.2012.6261229

Cook A, Hellebrand S, Wunderlich H-J. Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. In: 17th IEEE European Test Symposium (ETS’12). Annecy, France: IEEE; 2012:1-6. doi:10.1109/ets.2012.6233025

Cook A, Hellebrand S, Wunderlich H-J. Eingebaute Selbstdiagnose Mit Zufälligen Und Deterministischen Mustern. 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany; 2012.

Cook A, Hellebrand S, Indlekofer T, Wunderlich H-J. Diagnostic Test of Robust Circuits. In: 20th IEEE Asian Test Symposium (ATS’11). New Delhi, India: IEEE; 2011:285-290. doi:10.1109/ats.2011.55

Polian I, Becker B, Hellebrand S, Wunderlich H-J, Maxwell P. Towards Variation-Aware Test Methods. In: 16th IEEE European Test Symposium Trondheim (ETS’11). Trondheim, Norway: IEEE; 2011. doi:10.1109/ets.2011.51

Cook A, Hellebrand S, Indlekofer T, Wunderlich H-J. Robuster Selbsttest mit Diagnose. In: 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf.” Hamburg, Germany; 2011:48-53.

Hopsch F, Becker B, Hellebrand S, et al. Variation-Aware Fault Modeling. SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer. 2011;54(4):1813-1826.

Kamran A, Nemati N, Sadeghi-Kohan S, Navabi Z. Virtual tester development using HDL/PLI. In: 2010 East-West Design &;amp; Test Symposium (EWDTS). IEEE; 2011. doi:10.1109/ewdts.2010.5742156

Fröse V, Ibers R, Hellebrand S. Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany; 2010.

Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10). Chicago, IL, USA: IEEE; 2010. doi:10.1109/dsnw.2010.5542612

Hunger M, Hellebrand S. Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” Wildbad Kreuth, Germany; 2010:81-88.

Hellebrand S. Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180; 2010.

Hopsch F, Becker B, Hellebrand S, et al. Variation-Aware Fault Modeling. In: 19th IEEE Asian Test Symposium (ATS’10). IEEE; 2010:87-93. doi:10.1109/ats.2010.24

Indlekofer T, Schnittger M, Hellebrand S. Efficient Test Response Compaction for Robust BIST Using Parity Sequences. In: 28th IEEE International Conference on Computer Design (ICCD’10). IEEE; 2010:480-485. doi:10.1109/iccd.2010.5647648

Hunger M, Hellebrand S. The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10). IEEE; 2010:101-108. doi:10.1109/dft.2010.19

Froese V, Ibers R, Hellebrand S. Reusing NoC-Infrastructure for Test Data Compression. In: 28th IEEE VLSI Test Symposium (VTS’10). IEEE; 2010:227-231. doi:10.1109/vts.2010.5469570

Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper). ; 2010.

Indlekofer T, Schnittger M, Hellebrand S. Robuster Selbsttest mit extremer Kompaktierung. In: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2010:17-24.

Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. ATPG-Based Grading of Strong Fault-Secureness. In: 15th IEEE International On-Line Testing Symposium (IOLTS’09. IEEE; 2009. doi:10.1109/iolts.2009.5196027

Hellebrand S, Hunger M. Are Robust Circuits Really Robust? In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk). IEEE; 2009:77. doi:10.1109/dft.2009.28

Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. In: 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2009.

Coym T, Hellebrand S, Ludwig S, Straube B, Wunderlich H-J, G. Zoellin C. Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich; 2008.

Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich; 2008.

Oehler P, Bosio A, di Natale G, Hellebrand S. A Modular Memory BIST for Optimized Memory Repair. In: 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster). IEEE; 2008. doi:10.1109/iolts.2008.30

Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Signature Rollback - A Technique for Testing Robust Circuits. In: 26th IEEE VLSI Test Symposium (VTS’08). IEEE; 2008:125-130. doi:10.1109/vts.2008.34

Hunger M, Hellebrand S. Verification and Analysis of Self-Checking Properties through ATPG. In: 14th IEEE International On-Line Testing Symposium (IOLTS’08). IEEE; 2008. doi:10.1109/iolts.2008.32

Hunger M, Hellebrand S. Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. In: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2008.

Oehler P, Bosio A, Di Natale G, Hellebrand S. Modularer Selbsttest und optimierte Reparaturanalyse. In: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2008.

Hellebrand S. Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 5th IEEE East-West Design \'26; Test Symposium, Yerevan, Armenia (Invited Talk); 2007.

Ali M, Welzl M, Hessler S, Hellebrand S. An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster); 2007.

Oehler P, Hellebrand S, Wunderlich H-J. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany; 2007.

Hellebrand S. Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany; 2007.

Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07). IEEE; 2007:50-58. doi:10.1109/dft.2007.43

Oehler P, Hellebrand S, Wunderlich H-J. Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. In: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07). IEEE; 2007:185-190. doi:10.1109/ddecs.2007.4295278

Oehler P, Hellebrand S, Wunderlich H-J. An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. In: 12th IEEE European Test Symposium (ETS’07). IEEE; 2007:91-96. doi:10.1109/ets.2007.10

Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. In: 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper). ; 2007.

Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. Informacije MIDEM, Ljubljana (Invited Paper). 2007;37(4 (124)):212-219.

Ali M, Hessler S, Welzl M, Hellebrand S. An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip. International Journal on High Performance Systems Architecture. 2007;1(2):113-123.

Ali M, Welzl M, Hessler S, Hellebrand S. A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip. In: 4th International Conference on Information Technology: New Generations (ITNG’07). ; 2007:1027-1032.

Becker B, Polian I, Hellebrand S, Straube B, Wunderlich H-J. Test und Zuverlässigkeit nanoelektronischer Systeme. In: 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2007.

Becker B, Polian I, Hellebrand S, Straube B, Wunderlich H-J. DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme. it - Information Technology. 2006;48(5):305-311.

Oehler P, Hellebrand S. A Low Power Design for Embedded DRAMs with Online Consistency Checking. Kleinheubachertagung 2005, Miltenberg, Germany; 2005.

Ali M, Welzl M, Hellebrand S. Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria; 2005.

Oehler P, Hellebrand S. Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria; 2005.

Ali M, Welzl M, Zwicknagl M, Hellebrand S. Considerations for Fault-Tolerant Networks on Chips. In: IEEE International Conference on Microelectronics (ICM’05). IEEE; 2005. doi:10.1109/icm.2005.1590063

Oehler P, Hellebrand S. Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. In: 10th IEEE European Test Symposium (ETS’05). IEEE; 2005:148-153. doi:10.1109/ets.2005.28

Ali M, Welzl M, Hellebrand S. A Dynamic Routing Mechanism for Network on Chip. In: 23rd IEEE NORCHIP Conference. IEEE; 2005:70-73. doi:10.1109/norchp.2005.1596991

Liu Jing M, Ruehrup S, Schindelhauer C, et al. Sensor Networks with More Features Using Less Hardware. In: GOR/NGB Conference Tilburg 2004. Tilburg, Netherlands; 2004.

Breu R, Fahringer T, Fensel D, Hellebrand S, Middeldorp A, Scherzer O. Im Westen Viel Neues - Informatik an Der Universität Innsbruck. OCG Journal, pp. 28-29; 2004.

Hellebrand S, Wuertenberger A, S. Tautermann C. Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France; 2004.

Wuertenberger A, S. Tautermann C, Hellebrand S. Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. In: IEEE International Test Conference (ITC’04). IEEE; 2004:926-935. doi:10.1109/test.2004.1387357

Breu R, Hellebrand S, Welzl M. Experiences from Teaching Software Development in a Java Environment. Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia; 2003.

Wuertenberger A, S. Tautermann C, Hellebrand S. A Hybrid Coding Strategy for Optimized Test Data Compression. In: IEEE International Test Conference (ITC’03). IEEE; 2003:451-459. doi:10.1109/test.2003.1270870

Hellebrand S, Wuertenberger A. Alternating Run-Length Coding: A Technique for Improved Test Data Compression. IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA; 2002.

Hellebrand S, Wunderlich H-J, A. Ivaniuk A, V. Klimets Y, N. Yarmolik V. Efficient Online and Offline Testing of Embedded DRAMs. IEEE Transactions on Computers. 2002;51(7):801-809. doi:10.1109/tc.2002.1017700

Hellebrand S, Liang H-G, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Journal of Electronic Testing - Theory and Applications (JETTA). 2002;18(2):157-168.

Liang H, Hellebrand S, Wunderlich H-J. A Mixed-Mode BIST Scheme Based on Folding Compression. Journal on Computer Science and Technology. 2002;17(2):203-212.

Liang H-G, Hellebrand S, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE European Test Workshop, Stockholm, Sweden; 2001.

Liang H-G, Hellebrand S, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. In: IEEE International Test Conference (ITC’01). IEEE; 2001:894-902. doi:10.1109/test.2001.966712

Liang H-G, Hellebrand S, Wunderlich H-J. Deterministic BIST Scheme Based on Reseeding of Folding Counters. Journal of Computer Research and Development, (Jisuanji Yanjiu yu Fazhan). 2001;38(8):931.

Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Journal of Electronic Testing - Theory and Applications (JETTA). 2001;17(3/4):341-349.

Hellebrand S, Wunderlich H-J. Hardwarepraktikum Im Diplomstudiengang Informatik. Handbuch Lehre, Berlin, Raabe Verlag; 2000.

Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE European Test Workshop, Cascais, Portugal; 2000.

Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. In: IEEE International Test Conference (ITC’00). IEEE; 2000:778-784. doi:10.1109/test.2000.894274

Hellebrand S. Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren. Verlag Dr. Kovac, Hamburg: Verlag Dr. Kovac, Hamburg; 1999.

Hellebrand S, Wunderlich H-J, N. Yarmolik V. Exploiting Symmetries to Speed Up Transparent BIST. 11th GI/ITG/GMM/IEEE Workshop; 1999.

Hellebrand S, Wunderlich H-J, A. Ivaniuk A, V. Klimets Y, N. Yarmolik V. Error Detecting Refreshment for Embedded DRAMs. In: 17th IEEE VLSI Test Symposium (VTS’99). IEEE; 1999:384-390. doi:10.1109/vtest.1999.766693

N. Yarmolik V, V. Bykov I, Hellebrand S, Wunderlich H-J. Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. In: Third European Dependable Computing Conference (EDCC-3). ; 1999.

Hellebrand S, Wunderlich H-J, N. Yarmolik V. Symmetric Transparent BIST for RAMs. In: Design Automation and Test in Europe (DATE’99). ; 1999:702-707.

Hellebrand S, Wunderlich H-J. Test Und Synthese Schneller Eingebetteter Systeme. Universität Stuttgart; 1998.

N. Yarmolik V, Hellebrand S, Wunderlich H-J. Efficient Consistency Checking for Embedded Memories. 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA; 1998.

N. Yarmolik V, Hellebrand S, Wunderlich H-J. Efficient Consistency Checking for Embedded Memories. 10th GI/ITG/GMM/IEEE Workshop; 1998.

Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. In: Mixed-Mode BIST Using Embedded Processors. 5. Kluwer Academic Publishers; 1998.

Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. Journal of Electronic Testing Theory and Applications - JETTA. 1998;12(1/2):127-138.

Hellebrand S, Hertwig A, Wunderlich H-J. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. IEEE Design and Test. 1998;15(4):36-41.

Hertwig A, Hellebrand S, Wunderlich H-J. Fast Self-Recovering Controllers. In: 16th IEEE VLSI Test Symposium (VTS’98). IEEE; 1998:296-302. doi:10.1109/vtest.1998.670883

Hellebrand S, Wunderlich H-J, N. Yarmolik V. Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. In: Design Automation and Test in Europe (DATE’98). ; 1998:173-179. doi:10.1109/date.1998.655853

N. Yarmolik V, V. Klimets Y, Hellebrand S, Wunderlich H-J. New Transparent RAM BIST Based on Self-Adjusting Output Data Compression. In: Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’98). ; 1998:27-33.

Tsai K-H, Hellebrand S, Rajski J, Marek-Sadowska M. STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA; 1997.

Hertwig A, Hellebrand S, Wunderlich H-J. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 3rd IEEE International On-Line Testing Workshop, Crete, Greece; 1997.

Tsai K-H, Hellebrand S, Marek-Sadowska M, Rajski J. STARBIST: Scan Autocorrelated Random Pattern Generation. In: 34th ACM/IEEE Design Automation Conference (DAC’97). IEEE; 1997. doi:10.1109/dac.1997.597194

Hellebrand S, Wunderlich H-J. Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA; 1996.

Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France; 1996.

Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. In: IEEE International Test Conference (ITC’96). IEEE; 1996:195-204. doi:10.1109/test.1996.556962

Hellebrand S, Wunderlich H-J. Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany; 1995.

Hellebrand S, Wunderlich H-J, Goncalves F, Paulo Teixeira J. Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany; 1995.

Hellebrand S, Herzog M, Wunderlich H-J. Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany; 1995.

Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J. Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA; 1995.

Hellebrand S, Rajski J, Tarnick S, Venkataraman S, Courtois B. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Transactions on Computers. 1995;44(2):223-233. doi:10.1109/12.364534

Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J. Pattern Generation for a Deterministic BIST Scheme. In: ACM/IEEE International Conference on Computer Aided Design (ICCAD’95). IEEE; 1995:88-94. doi:10.1109/iccad.1995.479997

Hellebrand S, Juergensen A, Wunderlich H-J. Synthesis for Off-Line Testability. University of Siegen, Germany; 1994.

Hellebrand S, Juergensen A, Stroele A, Wunderlich H-J. Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany; 1994.

Venkataraman S, Rajski J, Hellebrand S, Tarnick S. Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands; 1994.

Hellebrand S, Wunderlich H-J. Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands; 1994.

Hellebrand S, Paulo Teixeira J, Wunderlich H-J. Synthesis for Testability - the ARCHIMEDES Approach. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA; 1994.

Hellebrand S, Wunderlich H-J. An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. In: ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94). IEEE; 1994:110-116. doi:10.1109/iccad.1994.629752

Hellebrand S, Wunderlich H-J. Synthese schneller selbsttestbarer Steuerwerke. In: Tagungsband Der GI/GME/ITG-Fachtagung \'26; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme. ; 1994:3-11.

Hellebrand S, Wunderlich H-J. Synthesis of Self-Testable Controllers. In: European Design and Test Conference (EDAC/ETC/EUROASIC). ; 1994:580-585. doi:10.1109/edtc.1994.326815

Hellebrand S, Tarnick S, Rajski J, Courtois B. Effiziente Erzeugung Deterministischer Muster Im Selbsttest. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany; 1993.

Hellebrand S, Wunderlich H-J. Synthesis of Self-Testable Controllers. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France; 1993.