Cook, A., Hellebrand, S., E. Imhof, M., Mumtaz, A., &; Wunderlich, H.-J. (2012). Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. In 13th IEEE Latin American Test Workshop (LATW’12) (pp. 1–4). Quito, Ecuador: IEEE.https://doi.org/10.1109/latw.2012.6261229 

Cook, A., Hellebrand, S., &; Wunderlich, H.-J. (2012). Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. In 17th IEEE European Test Symposium (ETS’12) (pp. 1–6). Annecy, France: IEEE.https://doi.org/10.1109/ets.2012.6233025 

Cook, A., Hellebrand, S., &; Wunderlich, H.-J. (2012). Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern. 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany.

Cook, A., Hellebrand, S., Indlekofer, T., &; Wunderlich, H.-J. (2011). Diagnostic Test of Robust Circuits. In 20th IEEE Asian Test Symposium (ATS’11) (pp. 285–290). New Delhi, India: IEEE.https://doi.org/10.1109/ats.2011.55 

Polian, I., Becker, B., Hellebrand, S., Wunderlich, H.-J., &; Maxwell, P. (2011). Towards Variation-Aware Test Methods. In 16th IEEE European Test Symposium Trondheim (ETS’11). Trondheim, Norway: IEEE.https://doi.org/10.1109/ets.2011.51 

Cook, A., Hellebrand, S., Indlekofer, T., &; Wunderlich, H.-J. (2011). Robuster Selbsttest mit Diagnose. In 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit und Entwurf” (pp. 48–53). Hamburg, Germany.

Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2011). Variation-Aware Fault Modeling. SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer, 54(4), 1813–1826.

Kamran, A., Nemati, N., Sadeghi-Kohan, S., &; Navabi, Z. (2011). Virtual tester development using HDL/PLI. 2010 East-West Design &;amp; Test Symposium (EWDTS).https://doi.org/10.1109/ewdts.2010.5742156 

Fröse, V., Ibers, R., &; Hellebrand, S. (2010). Testdatenkompression mit Hilfe der Netzwerkinfrastruktur. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany.

Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10). Chicago, IL, USA: IEEE.https://doi.org/10.1109/dsnw.2010.5542612 

Hunger, M., &; Hellebrand, S. (2010). Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf” (pp. 81–88). Wildbad Kreuth, Germany.

Hellebrand, S. (2010). Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180.

Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2010). Variation-Aware Fault Modeling. 19th IEEE Asian Test Symposium (ATS’10), 87–93.https://doi.org/10.1109/ats.2010.24 

Indlekofer, T., Schnittger, M., &; Hellebrand, S. (2010). Efficient Test Response Compaction for Robust BIST Using Parity Sequences. 28th IEEE International Conference on Computer Design (ICCD’10), 480–485.https://doi.org/10.1109/iccd.2010.5647648 

Hunger, M., &; Hellebrand, S. (2010). The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 101–108.https://doi.org/10.1109/dft.2010.19 

Froese, V., Ibers, R., &; Hellebrand, S. (2010). Reusing NoC-Infrastructure for Test Data Compression. 28th IEEE VLSI Test Symposium (VTS’10), 227–231.https://doi.org/10.1109/vts.2010.5469570 

Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper).

Indlekofer, T., Schnittger, M., &; Hellebrand, S. (2010). Robuster Selbsttest mit extremer Kompaktierung. 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 17–24.

Hunger, M., Hellebrand, S., Czutro, A., Polian, I., &; Becker, B. (2009). ATPG-Based Grading of Strong Fault-Secureness. 15th IEEE International On-Line Testing Symposium (IOLTS’09.https://doi.org/10.1109/iolts.2009.5196027 

Hellebrand, S., &; Hunger, M. (2009). Are Robust Circuits Really Robust? 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 77.https://doi.org/10.1109/dft.2009.28 

Hunger, M., Hellebrand, S., Czutro, A., Polian, I., &; Becker, B. (2009). Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”

Coym, T., Hellebrand, S., Ludwig, S., Straube, B., Wunderlich, H.-J., &; G. Zoellin, C. (2008). Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich.

Amgalan, U., Hachmann, C., Hellebrand, S., &; Wunderlich, H.-J. (2008). Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich.

Oehler, P., Bosio, A., di Natale, G., &; Hellebrand, S. (2008). A Modular Memory BIST for Optimized Memory Repair. 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster).https://doi.org/10.1109/iolts.2008.30 

Amgalan, U., Hachmann, C., Hellebrand, S., &; Wunderlich, H.-J. (2008). Signature Rollback - A Technique for Testing Robust Circuits. 26th IEEE VLSI Test Symposium (VTS’08), 125–130.https://doi.org/10.1109/vts.2008.34 

Hunger, M., &; Hellebrand, S. (2008). Verification and Analysis of Self-Checking Properties through ATPG. 14th IEEE International On-Line Testing Symposium (IOLTS’08).https://doi.org/10.1109/iolts.2008.32 

Hunger, M., &; Hellebrand, S. (2008). Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”

Oehler, P., Bosio, A., Di Natale, G., &; Hellebrand, S. (2008). Modularer Selbsttest und optimierte Reparaturanalyse. 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”

Hellebrand, S. (2007). Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 5th IEEE East-West Design \'26; Test Symposium, Yerevan, Armenia (Invited Talk).

Ali, M., Welzl, M., Hessler, S., &; Hellebrand, S. (2007). An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster).

Oehler, P., Hellebrand, S., &; Wunderlich, H.-J. (2007). An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany.

Hellebrand, S. (2007). Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany.

Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., &; Straube, B. (2007). A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), 50–58.https://doi.org/10.1109/dft.2007.43 

Oehler, P., Hellebrand, S., &; Wunderlich, H.-J. (2007). Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 185–190.https://doi.org/10.1109/ddecs.2007.4295278 

Oehler, P., Hellebrand, S., &; Wunderlich, H.-J. (2007). An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. 12th IEEE European Test Symposium (ETS’07), 91–96.https://doi.org/10.1109/ets.2007.10 

Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., &; Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper).

Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., &; Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. Informacije MIDEM, Ljubljana (Invited Paper), 37(4 (124)), 212–219.

Ali, M., Hessler, S., Welzl, M., &; Hellebrand, S. (2007). An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip. International Journal on High Performance Systems Architecture, 1(2), 113–123.

Ali, M., Welzl, M., Hessler, S., &; Hellebrand, S. (2007). A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip. 4th International Conference on Information Technology: New Generations (ITNG’07), 1027–1032.

Becker, B., Polian, I., Hellebrand, S., Straube, B., &; Wunderlich, H.-J. (2007). Test und Zuverlässigkeit nanoelektronischer Systeme. 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”

Becker, B., Polian, I., Hellebrand, S., Straube, B., &; Wunderlich, H.-J. (2006). DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme. It - Information Technology, 48(5), 305–311.

Oehler, P., &; Hellebrand, S. (2005). A Low Power Design for Embedded DRAMs with Online Consistency Checking. Kleinheubachertagung 2005, Miltenberg, Germany.

Ali, M., Welzl, M., &; Hellebrand, S. (2005). Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria.

Oehler, P., &; Hellebrand, S. (2005). Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria.

Ali, M., Welzl, M., Zwicknagl, M., &; Hellebrand, S. (2005). Considerations for Fault-Tolerant Networks on Chips. IEEE International Conference on Microelectronics (ICM’05).https://doi.org/10.1109/icm.2005.1590063 

Oehler, P., &; Hellebrand, S. (2005). Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. 10th IEEE European Test Symposium (ETS’05), 148–153.https://doi.org/10.1109/ets.2005.28 

Ali, M., Welzl, M., &; Hellebrand, S. (2005). A Dynamic Routing Mechanism for Network on Chip. 23rd IEEE NORCHIP Conference, 70–73.https://doi.org/10.1109/norchp.2005.1596991 

Liu Jing, M., Ruehrup, S., Schindelhauer, C., Volbert, K., Dierkes, M., Bellgardt, A.,  Hilleringmann, U. (2004). Sensor Networks with More Features Using Less Hardware. In GOR/NGB Conference Tilburg 2004. Tilburg, Netherlands.

Breu, R., Fahringer, T., Fensel, D., Hellebrand, S., Middeldorp, A., &; Scherzer, O. (2004). Im Westen viel Neues - Informatik an der Universität Innsbruck. OCG Journal, pp. 28-29.

Hellebrand, S., Wuertenberger, A., &; S. Tautermann, C. (2004). Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France.

Wuertenberger, A., S. Tautermann, C., &; Hellebrand, S. (2004). Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. IEEE International Test Conference (ITC’04), 926–935.https://doi.org/10.1109/test.2004.1387357 

Breu, R., Hellebrand, S., &; Welzl, M. (2003). Experiences from Teaching Software Development in a Java Environment. Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia.

Wuertenberger, A., S. Tautermann, C., &; Hellebrand, S. (2003). A Hybrid Coding Strategy for Optimized Test Data Compression. IEEE International Test Conference (ITC’03), 451–459.https://doi.org/10.1109/test.2003.1270870 

Hellebrand, S., &; Wuertenberger, A. (2002). Alternating Run-Length Coding: A Technique for Improved Test Data Compression. IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA.

Hellebrand, S., Wunderlich, H.-J., A. Ivaniuk, A., V. Klimets, Y., &; N. Yarmolik, V. (2002). Efficient Online and Offline Testing of Embedded DRAMs. IEEE Transactions on Computers, 51(7), 801–809.https://doi.org/10.1109/tc.2002.1017700 

Hellebrand, S., Liang, H.-G., &; Wunderlich, H.-J. (2002). Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Journal of Electronic Testing - Theory and Applications (JETTA), 18(2), 157–168.

Liang, H., Hellebrand, S., &; Wunderlich, H.-J. (2002). A Mixed-Mode BIST Scheme Based on Folding Compression. Journal on Computer Science and Technology, 17(2), 203–212.

Liang, H.-G., Hellebrand, S., &; Wunderlich, H.-J. (2001). Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE European Test Workshop, Stockholm, Sweden.

Liang, H.-G., Hellebrand, S., &; Wunderlich, H.-J. (2001). Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE International Test Conference (ITC’01), 894–902.https://doi.org/10.1109/test.2001.966712 

Liang, H.-G., Hellebrand, S., &; Wunderlich, H.-J. (2001). Deterministic BIST Scheme Based on Reseeding of Folding Counters. Journal of Computer Research and Development, (Jisuanji Yanjiu Yu Fazhan), 38(8), 931.

Hellebrand, S., Liang, H.-G., &; Wunderlich, H.-J. (2001). A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Journal of Electronic Testing - Theory and Applications (JETTA), 17(3/4), 341–349.

Hellebrand, S., &; Wunderlich, H.-J. (2000). Hardwarepraktikum im Diplomstudiengang Informatik. Handbuch Lehre, Berlin, Raabe Verlag.

Hellebrand, S., Liang, H.-G., &; Wunderlich, H.-J. (2000). A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE European Test Workshop, Cascais, Portugal.

Hellebrand, S., Liang, H.-G., &; Wunderlich, H.-J. (2000). A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE International Test Conference (ITC’00), 778–784.https://doi.org/10.1109/test.2000.894274 

Hellebrand, S. (1999). Selbsttestbare Steuerwerke - Strukturen und Syntheseverfahren. Verlag Dr. Kovac, Hamburg: Verlag Dr. Kovac, Hamburg.

Hellebrand, S., Wunderlich, H.-J., &; N. Yarmolik, V. (1999). Exploiting Symmetries to Speed Up Transparent BIST. 11th GI/ITG/GMM/IEEE Workshop.

Hellebrand, S., Wunderlich, H.-J., A. Ivaniuk, A., V. Klimets, Y., &; N. Yarmolik, V. (1999). Error Detecting Refreshment for Embedded DRAMs. 17th IEEE VLSI Test Symposium (VTS’99), 384–390.https://doi.org/10.1109/vtest.1999.766693 

N. Yarmolik, V., V. Bykov, I., Hellebrand, S., &; Wunderlich, H.-J. (1999). Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. Third European Dependable Computing Conference (EDCC-3).

Hellebrand, S., Wunderlich, H.-J., &; N. Yarmolik, V. (1999). Symmetric Transparent BIST for RAMs. Design Automation and Test in Europe (DATE’99), 702–707.

Hellebrand, S., &; Wunderlich, H.-J. (1998). Test und Synthese schneller eingebetteter Systeme. Universität Stuttgart.

N. Yarmolik, V., Hellebrand, S., &; Wunderlich, H.-J. (1998). Efficient Consistency Checking for Embedded Memories. 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.

N. Yarmolik, V., Hellebrand, S., &; Wunderlich, H.-J. (1998). Efficient Consistency Checking for Embedded Memories. 10th GI/ITG/GMM/IEEE Workshop.

Hellebrand, S., Wunderlich, H.-J., &; Hertwig, A. (1998). Mixed-Mode BIST Using Embedded Processors. In Mixed-Mode BIST Using Embedded Processors. Kluwer Academic Publishers.

Hellebrand, S., Wunderlich, H.-J., &; Hertwig, A. (1998). Mixed-Mode BIST Using Embedded Processors. Journal of Electronic Testing Theory and Applications - JETTA, 12(1/2), 127–138.

Hellebrand, S., Hertwig, A., &; Wunderlich, H.-J. (1998). Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. IEEE Design and Test, 15(4), 36–41.

Hertwig, A., Hellebrand, S., &; Wunderlich, H.-J. (1998). Fast Self-Recovering Controllers. 16th IEEE VLSI Test Symposium (VTS’98), 296–302.https://doi.org/10.1109/vtest.1998.670883 

Hellebrand, S., Wunderlich, H.-J., &; N. Yarmolik, V. (1998). Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. Design Automation and Test in Europe (DATE’98), 173–179.https://doi.org/10.1109/date.1998.655853 

N. Yarmolik, V., V. Klimets, Y., Hellebrand, S., &; Wunderlich, H.-J. (1998). New Transparent RAM BIST Based on Self-Adjusting Output Data Compression. Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’98), 27–33.

Tsai, K.-H., Hellebrand, S., Rajski, J., &; Marek-Sadowska, M. (1997). STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.

Hertwig, A., Hellebrand, S., &; Wunderlich, H.-J. (1997). Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 3rd IEEE International On-Line Testing Workshop, Crete, Greece.

Tsai, K.-H., Hellebrand, S., Marek-Sadowska, M., &; Rajski, J. (1997). STARBIST: Scan Autocorrelated Random Pattern Generation. 34th ACM/IEEE Design Automation Conference (DAC’97).https://doi.org/10.1109/dac.1997.597194 

Hellebrand, S., &; Wunderlich, H.-J. (1996). Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA.

Hellebrand, S., Wunderlich, H.-J., &; Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France.

Hellebrand, S., Wunderlich, H.-J., &; Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. IEEE International Test Conference (ITC’96), 195–204.https://doi.org/10.1109/test.1996.556962 

Hellebrand, S., &; Wunderlich, H.-J. (1995). Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany.

Hellebrand, S., Wunderlich, H.-J., Goncalves, F., &; Paulo Teixeira, J. (1995). Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany.

Hellebrand, S., Herzog, M., &; Wunderlich, H.-J. (1995). Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany.

Hellebrand, S., Reeb, B., Tarnick, S., &; Wunderlich, H.-J. (1995). Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA.

Hellebrand, S., Rajski, J., Tarnick, S., Venkataraman, S., &; Courtois, B. (1995). Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Transactions on Computers, 44(2), 223–233.https://doi.org/10.1109/12.364534 

Hellebrand, S., Reeb, B., Tarnick, S., &; Wunderlich, H.-J. (1995). Pattern Generation for a Deterministic BIST Scheme. ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), 88–94.https://doi.org/10.1109/iccad.1995.479997 

Hellebrand, S., Juergensen, A., &; Wunderlich, H.-J. (1994). Synthesis for Off-line Testability. University of Siegen, Germany.

Hellebrand, S., Juergensen, A., Stroele, A., &; Wunderlich, H.-J. (1994). Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany.

Venkataraman, S., Rajski, J., Hellebrand, S., &; Tarnick, S. (1994). Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands.

Hellebrand, S., &; Wunderlich, H.-J. (1994). Ein Verfahren zur testfreundlichen Steuerwerkssynthese. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands.

Hellebrand, S., Paulo Teixeira, J., &; Wunderlich, H.-J. (1994). Synthesis for Testability - the ARCHIMEDES Approach. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.

Hellebrand, S., &; Wunderlich, H.-J. (1994). An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), 110–116.https://doi.org/10.1109/iccad.1994.629752 

Hellebrand, S., &; Wunderlich, H.-J. (1994). Synthese schneller selbsttestbarer Steuerwerke. Tagungsband Der GI/GME/ITG-Fachtagung \'26; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, 3–11.

Hellebrand, S., &; Wunderlich, H.-J. (1994). Synthesis of Self-Testable Controllers. European Design and Test Conference (EDAC/ETC/EUROASIC), 580–585.https://doi.org/10.1109/edtc.1994.326815 

Hellebrand, S., Tarnick, S., Rajski, J., &; Courtois, B. (1993). Effiziente Erzeugung deterministischer Muster im Selbsttest. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany.

Hellebrand, S., &; Wunderlich, H.-J. (1993). Synthesis of Self-Testable Controllers. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France.