V. N. Yarmolik, S. Hellebrand, and H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories. 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1998.
LibreCat: /record/13091

V. N. Yarmolik, S. Hellebrand, and H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories. 10th GI/ITG/GMM/IEEE Workshop, 1998.
LibreCat: /record/13092

S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,” in Mixed-Mode BIST Using Embedded Processors, In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998: Kluwer Academic Publishers, 1998.
LibreCat: /record/13060

S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,” Journal of Electronic Testing Theory and Applications - JETTA, vol. 12, no. 1/2, pp. 127–138, 1998.
LibreCat: /record/13061

S. Hellebrand, A. Hertwig, and H.-J. Wunderlich, “Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications,” IEEE Design and Test, vol. 15, no. 4, pp. 36–41, 1998.
LibreCat: /record/13064

A. Hertwig, S. Hellebrand, and H.-J. Wunderlich, “Fast Self-Recovering Controllers,”10.1109/vtest.1998.670883__in 16th IEEE VLSI Test Symposium (VTS’98), 1998, pp. 296–302, doi:10.1109/vtest.1998.670883 .
LibreCat: /record/13007
DOI: 10.1109/vtest.1998.670883

S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, “Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs,”10.1109/date.1998.655853__in Design Automation and Test in Europe (DATE’98), 1998, pp. 173–179, doi:10.1109/date.1998.655853 .
LibreCat: /record/13008
DOI: 10.1109/date.1998.655853

V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, and H.-J. Wunderlich, “New Transparent RAM BIST Based on Self-Adjusting Output Data Compression,” in Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’98), 1998, pp. 27–33.
LibreCat: /record/13063

K.-H. Tsai, S. Hellebrand, J. Rajski, and M. Marek-Sadowska, STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1997.
LibreCat: /record/13089

A. Hertwig, S. Hellebrand, and H.-J. Wunderlich, Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.
LibreCat: /record/13090

K.-H. Tsai, S. Hellebrand, M. Marek-Sadowska, and J. Rajski, “STARBIST: Scan Autocorrelated Random Pattern Generation,”10.1109/dac.1997.597194__1997, doi:10.1109/dac.1997.597194 .
LibreCat: /record/13009
DOI: 10.1109/dac.1997.597194

S. Hellebrand and H.-J. Wunderlich, Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1996.
LibreCat: /record/13087

S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France, 1996.
LibreCat: /record/13088

S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,”10.1109/test.1996.556962__in IEEE International Test Conference (ITC’96), 1996, pp. 195–204, doi:10.1109/test.1996.556962 .
LibreCat: /record/13010
DOI: 10.1109/test.1996.556962

S. Hellebrand and H.-J. Wunderlich, Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany, 1995.
LibreCat: /record/13026

S. Hellebrand, H.-J. Wunderlich, F. Goncalves, and J. Paulo Teixeira, Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany, 1995.
LibreCat: /record/13027

S. Hellebrand, M. Herzog, and H.-J. Wunderlich, Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany, 1995.
LibreCat: /record/13028

S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich, Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1995.
LibreCat: /record/13086

S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,”10.1109/12.364534__IEEE Transactions on Computers, vol. 44, no. 2, pp. 223–233, 1995, doi:10.1109/12.364534 .
LibreCat: /record/13011
DOI: 10.1109/12.364534

S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich, “Pattern Generation for a Deterministic BIST Scheme,”10.1109/iccad.1995.479997__in ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), 1995, pp. 88–94, doi:10.1109/iccad.1995.479997 .
LibreCat: /record/13012
DOI: 10.1109/iccad.1995.479997