Tsai, K.-H., Hellebrand, S., Marek-Sadowska, M., &; Rajski, J. (1997). STARBIST: Scan Autocorrelated Random Pattern Generation. 34th ACM/IEEE Design Automation Conference (DAC’97).https://doi.org/10.1109/dac.1997.597194 
LibreCat: /record/13009
DOI: 10.1109/dac.1997.597194

Hellebrand, S., &; Wunderlich, H.-J. (1996). Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA.
LibreCat: /record/13087

Hellebrand, S., Wunderlich, H.-J., &; Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France.
LibreCat: /record/13088

Hellebrand, S., Wunderlich, H.-J., &; Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. IEEE International Test Conference (ITC’96), 195–204.https://doi.org/10.1109/test.1996.556962 
LibreCat: /record/13010
DOI: 10.1109/test.1996.556962

Hellebrand, S., &; Wunderlich, H.-J. (1995). Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany.
LibreCat: /record/13026

Hellebrand, S., Wunderlich, H.-J., Goncalves, F., &; Paulo Teixeira, J. (1995). Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany.
LibreCat: /record/13027

Hellebrand, S., Herzog, M., &; Wunderlich, H.-J. (1995). Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany.
LibreCat: /record/13028

Hellebrand, S., Reeb, B., Tarnick, S., &; Wunderlich, H.-J. (1995). Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA.
LibreCat: /record/13086

Hellebrand, S., Rajski, J., Tarnick, S., Venkataraman, S., &; Courtois, B. (1995). Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Transactions on Computers, 44(2), 223–233.https://doi.org/10.1109/12.364534 
LibreCat: /record/13011
DOI: 10.1109/12.364534

Hellebrand, S., Reeb, B., Tarnick, S., &; Wunderlich, H.-J. (1995). Pattern Generation for a Deterministic BIST Scheme. ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), 88–94.https://doi.org/10.1109/iccad.1995.479997 
LibreCat: /record/13012
DOI: 10.1109/iccad.1995.479997

Hellebrand, S., Juergensen, A., &; Wunderlich, H.-J. (1994). Synthesis for Off-line Testability. University of Siegen, Germany.
LibreCat: /record/13024

Hellebrand, S., Juergensen, A., Stroele, A., &; Wunderlich, H.-J. (1994). Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany.
LibreCat: /record/13025

Venkataraman, S., Rajski, J., Hellebrand, S., &; Tarnick, S. (1994). Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands.
LibreCat: /record/13083

Hellebrand, S., &; Wunderlich, H.-J. (1994). Ein Verfahren zur testfreundlichen Steuerwerkssynthese. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands.
LibreCat: /record/13084

Hellebrand, S., Paulo Teixeira, J., &; Wunderlich, H.-J. (1994). Synthesis for Testability - the ARCHIMEDES Approach. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.
LibreCat: /record/13085

Hellebrand, S., &; Wunderlich, H.-J. (1994). An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), 110–116.https://doi.org/10.1109/iccad.1994.629752 
LibreCat: /record/13014
DOI: 10.1109/iccad.1994.629752

Hellebrand, S., &; Wunderlich, H.-J. (1994). Synthese schneller selbsttestbarer Steuerwerke. Tagungsband Der GI/GME/ITG-Fachtagung \'26; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, 3–11.
LibreCat: /record/13059

Hellebrand, S., &; Wunderlich, H.-J. (1994). Synthesis of Self-Testable Controllers. European Design and Test Conference (EDAC/ETC/EUROASIC), 580–585.https://doi.org/10.1109/edtc.1994.326815 
LibreCat: /record/13013
DOI: 10.1109/edtc.1994.326815

Hellebrand, S., Tarnick, S., Rajski, J., &; Courtois, B. (1993). Effiziente Erzeugung deterministischer Muster im Selbsttest. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany.
LibreCat: /record/13081

Hellebrand, S., &; Wunderlich, H.-J. (1993). Synthesis of Self-Testable Controllers. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France.
LibreCat: /record/13082