Hellebrand, S., Juergensen, A., &; Wunderlich, H.-J. (1994). Synthesis for Off-line Testability. University of Siegen, Germany.
LibreCat: /record/13024

Hellebrand, S., Juergensen, A., Stroele, A., &; Wunderlich, H.-J. (1994). Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany.
LibreCat: /record/13025

Venkataraman, S., Rajski, J., Hellebrand, S., &; Tarnick, S. (1994). Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands.
LibreCat: /record/13083

Hellebrand, S., &; Wunderlich, H.-J. (1994). Ein Verfahren zur testfreundlichen Steuerwerkssynthese. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands.
LibreCat: /record/13084

Hellebrand, S., Paulo Teixeira, J., &; Wunderlich, H.-J. (1994). Synthesis for Testability - the ARCHIMEDES Approach. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.
LibreCat: /record/13085

Hellebrand, S., &; Wunderlich, H.-J. (1994). An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), 110–116.https://doi.org/10.1109/iccad.1994.629752 
LibreCat: /record/13014
DOI: 10.1109/iccad.1994.629752

Hellebrand, S., &; Wunderlich, H.-J. (1994). Synthese schneller selbsttestbarer Steuerwerke. Tagungsband Der GI/GME/ITG-Fachtagung \'26; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, 3–11.
LibreCat: /record/13059

Hellebrand, S., &; Wunderlich, H.-J. (1994). Synthesis of Self-Testable Controllers. European Design and Test Conference (EDAC/ETC/EUROASIC), 580–585.https://doi.org/10.1109/edtc.1994.326815 
LibreCat: /record/13013
DOI: 10.1109/edtc.1994.326815

Hellebrand, S., Tarnick, S., Rajski, J., &; Courtois, B. (1993). Effiziente Erzeugung deterministischer Muster im Selbsttest. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany.
LibreCat: /record/13081

Hellebrand, S., &; Wunderlich, H.-J. (1993). Synthesis of Self-Testable Controllers. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France.
LibreCat: /record/13082

Venkataraman, S., Rajski, J., Hellebrand, S., &; Tarnick, S. (1993). An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers. ACM/IEEE International Conference on Computer Aided Design (ICCAD’93).https://doi.org/10.1109/iccad.1993.580117 
LibreCat: /record/13015
DOI: 10.1109/iccad.1993.580117

Hellebrand, S., Tarnick, S., Rajski, J., &; Courtois, B. (1992). Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Institut National Polytechnique de Grenoble, Grenoble, France.
LibreCat: /record/13023

Hellebrand, S., Tarnick, S., Rajski, J., &; Courtois, B. (1992). Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. IEEE Design for Testability Workshop, Vail, CO, USA.
LibreCat: /record/13076

Hellebrand, S., Tarnick, S., Rajski, J., &; Courtois, B. (1992). Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Workshop on New Directions for Testing, Montreal, Canada.
LibreCat: /record/13080

Wunderlich, H.-J., &; Hellebrand, S. (1992). The Pseudoexhaustive Test of Sequential Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 11(1), 26–33.https://doi.org/10.1109/43.108616 
LibreCat: /record/13017
DOI: 10.1109/43.108616

Hellebrand, S., Tarnick, S., Rajski, J., &; Courtois, B. (1992). Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE International Test Conference (ITC’92), 120–129.https://doi.org/10.1109/test.1992.527812 
LibreCat: /record/13016
DOI: 10.1109/test.1992.527812

Hellebrand, S. (1991). Synthese vollständig testbarer Schaltungen. Verlag Düsseldorf: VDI Verlag: Verlag Düsseldorf: VDI Verlag.
LibreCat: /record/13034

Hellebrand, S., Wunderlich, H.-J., &; F. Haberl, O. (1990). Generating Pseudo-Exhaustive Vectors for External Testing. IEEE Design for Testability Workshop, Vail, CO, USA.
LibreCat: /record/13103

Hellebrand, S., &; Wunderlich, H.-J. (1990). Tools and Devices Supporting the Pseudo-Exhaustive Test. European Design Automation Conference (EDAC’90), 13–17.https://doi.org/10.1109/edac.1990.136612 
LibreCat: /record/13018
DOI: 10.1109/edac.1990.136612

Hellebrand, S., Wunderlich, H.-J., &; F. Haberl, O. (1990). Generating Pseudo-Exhaustive Vectors for External Testing. IEEE International Test Conference (ITC’90), 670–679.https://doi.org/10.1109/test.1990.114082 
LibreCat: /record/13019
DOI: 10.1109/test.1990.114082