Jafarzadeh, H., Klemme, F., Reimer, J. D., Najafi Haghi, Z. P.,  Amrouch, H., Hellebrand, S., &;  Wunderlich, H.-J. (2023). Robust Pattern Generation for Small Delay Faults under Process Variations. IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE International Test Conference (ITC’23), Anaheim, USA.
LibreCat: /record/45830

Sadeghi-Kohan, S., Hellebrand, S., &; Wunderlich, H.-J. (2022). Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing.https://doi.org/10.1007/s10836-021-05979-5 
LibreCat: /record/29351
DOI: 10.1007/s10836-021-05979-5

Sadeghi-Kohan, S., Hellebrand, S., &; Wunderlich, H.-J. (2022). EM-Aware Interconnect BIST. European Workshop on Silicon Lifecycle Management, March 18, 2022.
LibreCat: /record/29890

Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., &; Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020.
LibreCat: /record/19422

Sadeghi-Kohan, S., &; Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020.
LibreCat: /record/15419

Sadeghi-Kohan, S., &; Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 38th IEEE VLSI Test Symposium (VTS).https://doi.org/10.1109/vts48691.2020.9107591 
LibreCat: /record/29200
DOI: 10.1109/vts48691.2020.9107591

Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich, H.-J., &; Weng, X. (2020). Logic Fault Diagnosis of Hidden Delay Defects. IEEE International Test Conference (ITC’20), November 2020.
LibreCat: /record/19421

Maaz, M. U., Sprenger, A., &; Hellebrand, S. (2019). A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19).
LibreCat: /record/8112

Sprenger, A., &; Hellebrand, S. (2019). Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers, 28(1), 1–23.https://doi.org/10.1142/s0218126619400012 
LibreCat: /record/8667
DOI: 10.1142/s0218126619400012

Kampmann, M., A. Kochte, M., Liu, C., Schneider, E., Hellebrand, S., &; Wunderlich, H.-J. (2019). Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(10), 1956–1968.
LibreCat: /record/13048

Maaz, M. U., Sprenger, A., &; Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. 50th IEEE International Test Conference (ITC), 1–8.
LibreCat: /record/12918

Sprenger, A., &; Hellebrand, S. (2018). Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18).
LibreCat: /record/4576

Hellebrand, S., Henkel, J., Raghunathan, A., &; Wunderlich, H.-J. (2018). Guest Editors’ Introduction - Special Issue on Approximate Computing. IEEE Embedded Systems Letters, 10(1), 1–1.https://doi.org/10.1109/les.2018.2789942 
LibreCat: /record/12974
DOI: 10.1109/les.2018.2789942

Kampmann, M., &; Hellebrand, S. (2018). Design For Small Delay Test - A Simulation Study. Microelectronics Reliability, 80, 124–133.
LibreCat: /record/13057

Kampmann, M., &; Hellebrand, S. (2018). Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China.
LibreCat: /record/13072

Rezaeizadeh Rookerd, R., Sadeghi-Kohan, S., &; Navabi, Z. (2018). Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. Proceedings of the 2018 on Great Lakes Symposium on VLSI.https://doi.org/10.1145/3194554.3194599 
LibreCat: /record/29460
DOI: 10.1145/3194554.3194599

Sprenger, A., &; Hellebrand, S. (2018). Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &; Systems (DDECS).https://doi.org/10.1109/ddecs.2018.00020 
LibreCat: /record/4575
DOI: 10.1109/ddecs.2018.00020

Liu, C., Schneider, E., Kampmann, M., Hellebrand, S., &; Wunderlich, H.-J. (2018). Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. 27th IEEE Asian Test Symposium (ATS’18).https://doi.org/10.1109/ats.2018.00028 
LibreCat: /record/10575
DOI: 10.1109/ats.2018.00028

Sadeghi-Kohan, S., Vafaei, A., &; Navabi, Z. (2018). Near-Optimal Node Selection Procedure for Aging Monitor Placement. 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).https://doi.org/10.1109/iolts.2018.8474120 
LibreCat: /record/29459
DOI: 10.1109/iolts.2018.8474120

Deshmukh, J., Kunz, W., Wunderlich, H.-J., &; Hellebrand, S. (2017). Special Session on Early Life Failures. In 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE.https://doi.org/10.1109/vts.2017.7928933 
LibreCat: /record/12973
DOI: 10.1109/vts.2017.7928933

Kampmann, M., &; Hellebrand, S. (2017). X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz.
LibreCat: /record/13078

Kampmann, M., &; Hellebrand, S. (2017). Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. 20th IEEE International Symposium on Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’17).https://doi.org/10.1109/ddecs.2017.7934564 
LibreCat: /record/10576
DOI: 10.1109/ddecs.2017.7934564

Sadeghi-Kohan, S., Kamal, M., &; Navabi, Z. (2017). Self-Adjusting Monitor for Measuring Aging Rate and Advancement. IEEE Transactions on Emerging Topics in Computing, 8(3), 627–641.https://doi.org/10.1109/tetc.2017.2771441 
LibreCat: /record/29462
DOI: 10.1109/tetc.2017.2771441

Jenihhin, M., Kamkin, A., Navabi, Z., &; Sadeghi-Kohan, S. (2017). Universal mitigation of NBTI-induced aging by design randomization. 2016 IEEE East-West Design &; Test Symposium (EWDTS).https://doi.org/10.1109/ewdts.2016.7807635 
LibreCat: /record/29463
DOI: 10.1109/ewdts.2016.7807635

Kampmann, M., &; Hellebrand, S. (2016). X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. In 25th IEEE Asian Test Symposium (ATS’16) (pp. 1–6). Hiroshima, Japan: IEEE.https://doi.org/10.1109/ats.2016.20 
LibreCat: /record/12975
DOI: 10.1109/ats.2016.20

Kampmann, M., A. Kochte, M., Schneider, E., Indlekofer, T., Hellebrand, S., &; Wunderlich, H.-J. (2015). Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In 24th IEEE Asian Test Symposium (ATS’15) (pp. 109–114). Mumbai, India: IEEE.https://doi.org/10.1109/ats.2015.26 
LibreCat: /record/12976
DOI: 10.1109/ats.2015.26

Huang, Z., Liang, H., &; Hellebrand, S. (2015). A High Performance SEU Tolerant Latch. Journal of Electronic Testing - Theory and Applications (JETTA), 31(4), 349–359.
LibreCat: /record/13056

Hellebrand, S., Indlekofer, T., Kampmann, M., Kochte, M., Liu, C., &; Wunderlich, H.-J. (2015). Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany.
LibreCat: /record/13077

Sadeghi-Kohan, S., Kamran, A., Forooghifar, F., &; Navabi, Z. (2015). Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. 2015 10th International Conference on Design &; Technology of Integrated Systems in Nanoscale Era (DTIS).https://doi.org/10.1109/dtis.2015.7127373 
LibreCat: /record/29465
DOI: 10.1109/dtis.2015.7127373

Sadeghi-Kohan, S., Kamal, M., McNeil, J., Prinetto, P., &; Navabi, Z. (2015). Online self adjusting progressive age monitoring of timing variations. 2015 10th International Conference on Design &; Technology of Integrated Systems in Nanoscale Era (DTIS).https://doi.org/10.1109/dtis.2015.7127368 
LibreCat: /record/29466
DOI: 10.1109/dtis.2015.7127368

Hellebrand, S., Indlekofer, T., Kampmann, M., A. Kochte, M., Liu, C., &; Wunderlich, H.-J. (2014). FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In IEEE International Test Conference (ITC’14). Seattle, Washington, USA: IEEE.https://doi.org/10.1109/test.2014.7035360 
LibreCat: /record/12977
DOI: 10.1109/test.2014.7035360

Hellebrand, S., &; Wunderlich, H.-J. (2014). SAT-Based ATPG beyond Stuck-at Fault Testing. DeGruyter Journal on Information Technology (It), 56(4), 165–172.
LibreCat: /record/13054

Rodriguez Gomez, L., Cook, A., Indlekofer, T., Hellebrand, S., &; Wunderlich, H.-J. (2014). Adaptive Bayesian Diagnosis of Intermittent Faults. Journal of Electronic Testing - Theory and Applications (JETTA), 30(5), 527–540.
LibreCat: /record/13055

Alizadeh, B., Behnam, P., &; Sadeghi-Kohan, S. (2014). A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers, 1–1.https://doi.org/10.1109/tc.2014.2329687 
LibreCat: /record/46266
DOI: 10.1109/tc.2014.2329687

Mohammadi, M., Sadeghi-Kohan, S., Masoumi, N., &; Navabi, Z. (2014). An off-line MDSI interconnect BIST incorporated in BS 1149.1. 2014 19th IEEE European Test Symposium (ETS).https://doi.org/10.1109/ets.2014.6847847 
LibreCat: /record/46268
DOI: 10.1109/ets.2014.6847847

Sadeghi-Kohan, S., Behnam, P., Alizadeh, B., Fujita, M., &; Navabi, Z. (2014). Improving polynomial datapath debugging with HEDs. 2014 19th IEEE European Test Symposium (ETS).https://doi.org/10.1109/ets.2014.6847797 
LibreCat: /record/46267
DOI: 10.1109/ets.2014.6847797

Hellebrand, S. (2013). Analyzing and Quantifying Fault Tolerance Properties. In 14th IEEE Latin American Test Workshop - (LATW’13). Cordoba, Argentina: IEEE.https://doi.org/10.1109/latw.2013.6562662 
LibreCat: /record/12979
DOI: 10.1109/latw.2013.6562662

Cook, A., Rodriguez Gomez, L., Hellebrand, S., Indlekofer, T., &; Wunderlich, H.-J. (2013). Adaptive Test and Diagnosis of Intermittent Faults. 14th Latin American Test Workshop, Cordoba, Argentina.
LibreCat: /record/13075

Sadeghi-Kohan, S., Namaki-Shoushtari, M., Javaheri, F., &; Navabi, Z. (2013). BS 1149.1 extensions for an online interconnect fault detection and recovery. 2012 IEEE International Test Conference.https://doi.org/10.1109/test.2012.6401583 
LibreCat: /record/46271
DOI: 10.1109/test.2012.6401583

Sadeghi-Kohan, S., Keshavarz, S., Zokaee, F., Farahmandi, F., &; Navabi, Z. (2013). A new structure for interconnect offline testing. East-West Design &;amp; Test Symposium (EWDTS 2013).https://doi.org/10.1109/ewdts.2013.6673207 
LibreCat: /record/46270
DOI: 10.1109/ewdts.2013.6673207

Cook, A., Hellebrand, S., E. Imhof, M., Mumtaz, A., &; Wunderlich, H.-J. (2012). Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. In 13th IEEE Latin American Test Workshop (LATW’12) (pp. 1–4). Quito, Ecuador: IEEE.https://doi.org/10.1109/latw.2012.6261229 
LibreCat: /record/12980
DOI: 10.1109/latw.2012.6261229

Cook, A., Hellebrand, S., &; Wunderlich, H.-J. (2012). Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. In 17th IEEE European Test Symposium (ETS’12) (pp. 1–6). Annecy, France: IEEE.https://doi.org/10.1109/ets.2012.6233025 
LibreCat: /record/12981
DOI: 10.1109/ets.2012.6233025

Cook, A., Hellebrand, S., &; Wunderlich, H.-J. (2012). Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern. 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany.
LibreCat: /record/13074

Cook, A., Hellebrand, S., Indlekofer, T., &; Wunderlich, H.-J. (2011). Diagnostic Test of Robust Circuits. In 20th IEEE Asian Test Symposium (ATS’11) (pp. 285–290). New Delhi, India: IEEE.https://doi.org/10.1109/ats.2011.55 
LibreCat: /record/12982
DOI: 10.1109/ats.2011.55

Polian, I., Becker, B., Hellebrand, S., Wunderlich, H.-J., &; Maxwell, P. (2011). Towards Variation-Aware Test Methods. In 16th IEEE European Test Symposium Trondheim (ETS’11). Trondheim, Norway: IEEE.https://doi.org/10.1109/ets.2011.51 
LibreCat: /record/12984
DOI: 10.1109/ets.2011.51

Cook, A., Hellebrand, S., Indlekofer, T., &; Wunderlich, H.-J. (2011). Robuster Selbsttest mit Diagnose. In 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit und Entwurf” (pp. 48–53). Hamburg, Germany.
LibreCat: /record/13053

Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2011). Variation-Aware Fault Modeling. SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer, 54(4), 1813–1826.
LibreCat: /record/13052

Kamran, A., Nemati, N., Sadeghi-Kohan, S., &; Navabi, Z. (2011). Virtual tester development using HDL/PLI. 2010 East-West Design &;amp; Test Symposium (EWDTS).https://doi.org/10.1109/ewdts.2010.5742156 
LibreCat: /record/46272
DOI: 10.1109/ewdts.2010.5742156

Fröse, V., Ibers, R., &; Hellebrand, S. (2010). Testdatenkompression mit Hilfe der Netzwerkinfrastruktur. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany.
LibreCat: /record/10670

Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &; Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10). Chicago, IL, USA: IEEE.https://doi.org/10.1109/dsnw.2010.5542612 
LibreCat: /record/12987
DOI: 10.1109/dsnw.2010.5542612