V. N. Yarmolik, S. Hellebrand, and H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories. 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1998.
LibreCat: /record/13091

V. N. Yarmolik, S. Hellebrand, and H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories. 10th GI/ITG/GMM/IEEE Workshop, 1998.
LibreCat: /record/13092

S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,” in Mixed-Mode BIST Using Embedded Processors, In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998: Kluwer Academic Publishers, 1998.
LibreCat: /record/13060

S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,” Journal of Electronic Testing Theory and Applications - JETTA, vol. 12, no. 1/2, pp. 127–138, 1998.
LibreCat: /record/13061

S. Hellebrand, A. Hertwig, and H.-J. Wunderlich, “Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications,” IEEE Design and Test, vol. 15, no. 4, pp. 36–41, 1998.
LibreCat: /record/13064

A. Hertwig, S. Hellebrand, and H.-J. Wunderlich, “Fast Self-Recovering Controllers,”10.1109/vtest.1998.670883__in 16th IEEE VLSI Test Symposium (VTS’98), 1998, pp. 296–302, doi:10.1109/vtest.1998.670883 .
LibreCat: /record/13007
DOI: 10.1109/vtest.1998.670883

S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, “Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs,”10.1109/date.1998.655853__in Design Automation and Test in Europe (DATE’98), 1998, pp. 173–179, doi:10.1109/date.1998.655853 .
LibreCat: /record/13008
DOI: 10.1109/date.1998.655853

V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, and H.-J. Wunderlich, “New Transparent RAM BIST Based on Self-Adjusting Output Data Compression,” in Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’98), 1998, pp. 27–33.
LibreCat: /record/13063

K.-H. Tsai, S. Hellebrand, J. Rajski, and M. Marek-Sadowska, STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1997.
LibreCat: /record/13089

A. Hertwig, S. Hellebrand, and H.-J. Wunderlich, Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.
LibreCat: /record/13090

K.-H. Tsai, S. Hellebrand, M. Marek-Sadowska, and J. Rajski, “STARBIST: Scan Autocorrelated Random Pattern Generation,”10.1109/dac.1997.597194__1997, doi:10.1109/dac.1997.597194 .
LibreCat: /record/13009
DOI: 10.1109/dac.1997.597194

S. Hellebrand and H.-J. Wunderlich, Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1996.
LibreCat: /record/13087

S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France, 1996.
LibreCat: /record/13088

S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,”10.1109/test.1996.556962__in IEEE International Test Conference (ITC’96), 1996, pp. 195–204, doi:10.1109/test.1996.556962 .
LibreCat: /record/13010
DOI: 10.1109/test.1996.556962

S. Hellebrand and H.-J. Wunderlich, Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany, 1995.
LibreCat: /record/13026

S. Hellebrand, H.-J. Wunderlich, F. Goncalves, and J. Paulo Teixeira, Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany, 1995.
LibreCat: /record/13027

S. Hellebrand, M. Herzog, and H.-J. Wunderlich, Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany, 1995.
LibreCat: /record/13028

S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich, Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1995.
LibreCat: /record/13086

S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,”10.1109/12.364534__IEEE Transactions on Computers, vol. 44, no. 2, pp. 223–233, 1995, doi:10.1109/12.364534 .
LibreCat: /record/13011
DOI: 10.1109/12.364534

S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich, “Pattern Generation for a Deterministic BIST Scheme,”10.1109/iccad.1995.479997__in ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), 1995, pp. 88–94, doi:10.1109/iccad.1995.479997 .
LibreCat: /record/13012
DOI: 10.1109/iccad.1995.479997

S. Hellebrand, A. Juergensen, and H.-J. Wunderlich, Synthesis for Off-line Testability. University of Siegen, Germany, 1994.
LibreCat: /record/13024

S. Hellebrand, A. Juergensen, A. Stroele, and H.-J. Wunderlich, Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany, 1994.
LibreCat: /record/13025

S. Venkataraman, J. Rajski, S. Hellebrand, and S. Tarnick, Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.
LibreCat: /record/13083

S. Hellebrand and H.-J. Wunderlich, Ein Verfahren zur testfreundlichen Steuerwerkssynthese. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.
LibreCat: /record/13084

S. Hellebrand, J. Paulo Teixeira, and H.-J. Wunderlich, Synthesis for Testability - the ARCHIMEDES Approach. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1994.
LibreCat: /record/13085

S. Hellebrand and H.-J. Wunderlich, “An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures,”10.1109/iccad.1994.629752__in ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), 1994, pp. 110–116, doi:10.1109/iccad.1994.629752 .
LibreCat: /record/13014
DOI: 10.1109/iccad.1994.629752

S. Hellebrand and H.-J. Wunderlich, “Synthese schneller selbsttestbarer Steuerwerke,” in Tagungsband der GI/GME/ITG-Fachtagung \'26; Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1994, pp. 3–11.
LibreCat: /record/13059

S. Hellebrand and H.-J. Wunderlich, “Synthesis of Self-Testable Controllers,”10.1109/edtc.1994.326815__in European Design and Test Conference (EDAC/ETC/EUROASIC), 1994, pp. 580–585, doi:10.1109/edtc.1994.326815 .
LibreCat: /record/13013
DOI: 10.1109/edtc.1994.326815

S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, Effiziente Erzeugung deterministischer Muster im Selbsttest. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany, 1993.
LibreCat: /record/13081

S. Hellebrand and H.-J. Wunderlich, Synthesis of Self-Testable Controllers. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France, 1993.
LibreCat: /record/13082

S. Venkataraman, J. Rajski, S. Hellebrand, and S. Tarnick, “An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers,”10.1109/iccad.1993.580117__1993, doi:10.1109/iccad.1993.580117 .
LibreCat: /record/13015
DOI: 10.1109/iccad.1993.580117

S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Institut National Polytechnique de Grenoble, Grenoble, France, 1992.
LibreCat: /record/13023

S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. IEEE Design for Testability Workshop, Vail, CO, USA, 1992.
LibreCat: /record/13076

S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Workshop on New Directions for Testing, Montreal, Canada, 1992.
LibreCat: /record/13080

H.-J. Wunderlich and S. Hellebrand, “The Pseudoexhaustive Test of Sequential Circuits,”10.1109/43.108616__IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 11, no. 1, pp. 26–33, 1992, doi:10.1109/43.108616 .
LibreCat: /record/13017
DOI: 10.1109/43.108616

S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, “Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,”10.1109/test.1992.527812__in IEEE International Test Conference (ITC’92), 1992, pp. 120–129, doi:10.1109/test.1992.527812 .
LibreCat: /record/13016
DOI: 10.1109/test.1992.527812

S. Hellebrand, Synthese vollständig testbarer Schaltungen. Verlag Düsseldorf: VDI Verlag: Verlag Düsseldorf: VDI Verlag, 1991.
LibreCat: /record/13034

S. Hellebrand, H.-J. Wunderlich, and O. F. Haberl, Generating Pseudo-Exhaustive Vectors for External Testing. IEEE Design for Testability Workshop, Vail, CO, USA, 1990.
LibreCat: /record/13103

S. Hellebrand and H.-J. Wunderlich, “Tools and Devices Supporting the Pseudo-Exhaustive Test,”10.1109/edac.1990.136612__in European Design Automation Conference (EDAC’90), 1990, pp. 13–17, doi:10.1109/edac.1990.136612 .
LibreCat: /record/13018
DOI: 10.1109/edac.1990.136612

S. Hellebrand, H.-J. Wunderlich, and O. F. Haberl, “Generating Pseudo-Exhaustive Vectors for External Testing,”10.1109/test.1990.114082__in IEEE International Test Conference (ITC’90), 1990, pp. 670–679, doi:10.1109/test.1990.114082 .
LibreCat: /record/13019
DOI: 10.1109/test.1990.114082

H.-J. Wunderlich and S. Hellebrand, “The Pseudo-Exhaustive Test of Sequential Circuits,”10.1109/test.1989.82273__in IEEE International Test Conference (ITC’89), 1989, pp. 19–27, doi:10.1109/test.1989.82273 .
LibreCat: /record/13020
DOI: 10.1109/test.1989.82273

H.-J. Wunderlich and S. Hellebrand, “Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits,”10.1109/ftcs.1988.5294__in 18th International Symposium on Fault-Tolerant Computing, FTCS-18, 1988, pp. 36–45, doi:10.1109/ftcs.1988.5294 .
LibreCat: /record/13021
DOI: 10.1109/ftcs.1988.5294

D. Schmid, H.-J. Wunderlich, F. Feldbusch, S. Hellebrand, J. Holzinger, and A. Kunzmann, “Integrated Tools for Automatic Design for Testability,” in Tool Integration and Design Environments, F.J. Rammig (Editor), 1988, pp. 233–258.
LibreCat: /record/13058

S. Hellebrand and H.-J. Wunderlich, “Automatisierung des Entwurfs vollständig testbarer Schaltungen,” in GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188, 1988, pp. 145–159.
LibreCat: /record/13062

S. Hellebrand, Deformation dicker Punkte und Netze von Quadriken. Universität Regensburg, Fakultät für Mathematik, Regensburg, Germany, 1986.
LibreCat: /record/13022